Navid Azizi, Member of Technical Staff, Altera Corporation
Joshua Fender, Supervising Member of Technical Staff, Altera Corporation
Ryan Fung, Senior Member of Technical Staff, Altera Corporation

In an effort to increase their bandwidth, many ICs, such as memory interfaces, have been increasing the data rates at which they operate. To meet timing at these high data rates ICs are required to calibrate at power-up. Timing analysis of paths which are calibrated does not strictly meet the static timing analysis (STA) paradigm used predominately in EDA tools, and new methods are needed to accurately model them. This paper describes methods to obtain accurate timing of paths that are calibrated at runtime, and combines conventional STA with new methods to obtain timing that considers calibration, and effects after calibration.