Jianmin Zhang, Senior Signal Integrity Engineer, Cisco Systems
Martin Schauer, Principal Application Engineer, CST
Qinghua Bill Chen, Sr. Engineering Manager, Cisco Systems
Kelvin Qiu, Engineering Manager, Cisco Systems
Antonio Ciccomancini Scogna, Sr. Application Engineer, CST
Gerardo Romo, Application Engineer, CST

This paper presents modeling and realization of serial chip-to-chip communication beyond 25 Gbps. It will be shown that this can be achieved by techniques such as back-drilling via stubs, optimization of DC blocking via structures and application of VIPPO. Accurate modeling and performance prediction of high-speed channels are described in detail with different modeling alternatives. Channel segmentation is explored and guidelines for the given emerging application are presented. A study case consisting of two ASICs sitting on a 22-layer PCB aids as a test vehicle. Measurement and modeling is correlated up to 40 GHz for the high-speed channel under investigation.