Shishuang Sun, Member of Technical Staff Engineer, Altera Corporation
Larry D. Smith, Signal and Power Integrity Architect, Altera Corporation
Peter Boyle, Product Engineering Manager, Altera Corporation

On-chip PDN noise becomes a limiting factor in product performance as technology advances. Being able to predict the worst case and typical on-chip PDN noise is crucial for optimization of chip and package PDN early in the design phase. A test vehicle with an on-chip probe is built and measured. Switching current patterns for worst and typical core noise are determined. A generic PDN noise generation technique is proposed to represent a variety customer FPGA designs. A core logic current profile is developed and correlated to measurements. With measurements and what-if simulations, guidelines of mitigating on-chip PDN noise are discussed.