Jimmy Huat Since Huang, Power Delivery Engineer, Mobile Group, Intel
Tan Fern Nee, Power Integrity Engineer, Intel
Yong Lee Kee,, Structural Design Engineer, Intel
Ooi Poey Ling, Circuit Design Engineer, Intel
Pang Sze Geat, Power Integrity Engineer, Intel
Jess Kiu, Structural Design Engineer, Intel

For low-power design, power switch gate is introduced to the SOC to reduce the leakage current from the un-used IP block during power-saving mode. However, it introduces additional IR loss and reduces the voltage margin. It also induces huge current spike and pulls down the on-package voltage to almost zero during the switch gate turn-on transition to charge up the on-die decap. This paper demonstrates the full-path simulation and lab measurement to characterize the gated PDN behavior. Mitigation solution for the tight DC margin and on-package sudden voltage droop is provided. Good correlation between silicon and measurement is shown.