1. Chip-Level System Design Sample topics System architectures & partitioning Specification, constraints & design estimation Low-power strategies & implementation On-chip interconnects High-speed I/O design Clock & reset strategies Multi-abstraction modeling & languages Tools & tool flows for design Hardware/software co-design Hardware-dependent software Embedded processor design issues Hardware-dependent software Embedded processor design issues Design for test/verification (DFT, DFV) Design for manufacturing/yield (DFM, DFY) Design margining Simulation techniques & methodology Statistical modeling Variation-tolerant design Yield analysis and reliability On-chip debug design strategies On-chip instrumentation & measurement System-level time budgeting (Chip/SiP/SoC) Synthesis Timing closure Design optimization Chip to package pin I/O timing Electronic system level (ESL) design Platform-based design Mixed-signal design 2. Functional Verification Sample topics Pre-silicon verification of RTL, mixed-signal, and analog designs Post-silicon verification Verification planning & execution Driving verification from higher-level descriptions (e.g. ESL) Combining diverse approaches: simulation, emulation, formal, etc. Evaluating quality of verification coverage Verification of performance characteristics Verification frameworks, libraries, & reuse Verification flow engineering Verification languages & abstractions 3. IP Re-Use and Integration Sample topics Digital IP: processor, memory, I/O Analog, RF & other IP Commodity IP selection IP quality metrics Components of reusable IP Re-use methodology Reusable IP management (infrastructures) IP integration into products & systems IP test & debug IP verification Verifying IP designs Post-integration verification Verification IP IP protection IP standards Software considerations for hardware IP 4. System Co-Design: Chip/Package/Board Sample topics Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications) PCB/package/chip/device power modeling Power-grid modeling & analysis End-to-end link modeling Pin-out optimization, signal fan-out First- & second-level interconnect analysis Sub-system interaction System-level de-coupling strategy System-level power & signal integrity On-die signal/power integrity System noise modeling & mitigation Buffer modeling High-speed signaling, I/O interoperability Integrated optical links Merging of chip design and package design Mixed-signal system design Multi-voltage design Package modeling and measurement System-in-package (SiP), multi-chip package (MCP) design 5. PCB and Passive Component Technology Sample topics Advanced conductive and dielectric materials Impact of low copper surface roughness Microvias, RF vias & thermal vias High aspect-ratio vias Advanced laminate & PCB processing Interlayer connectivity alternatives Fine registration improvements Backdrilling methods & effects Electrical & mechanical co-design EM modeling of PCB traces & vias Embedded devices Passive & active devices Embedded optical channels Power delivery Fabrication: cost vs. performance Rigid-flex & multilayer flex circuit design & manufacturing Manufacturing impact on electrical properties Materials modeling Sockets & connectors Thermal characterization Via pin-field design 6. High-Speed Parallel Interface Design Sample topics System/FPGA/ASIC timing closure Timing analysis methodologies Statistical timing, bit error rate analysis Designing with dynamically aligned timing Signal integrity simulation High speed I/O modeling Crosstalk Modeling & incorporating effects of SSO Signal slew rate & impact on timing Designing with impedance controlled buffers/on-die termination Differential vs. single-ended signaling Performance vs. power vs. signal integrity Rules-based design Developing & managing high-speed layout rules Standards-based design (DDR2/3, HyperTransport 3.0, PCI-X, SPI 4.2 …) Developing standard design specifications & budgets Design margin vs. complexity vs. cost High-speed cable design, analysis & modeling Parallel nterconnect signal conditioning techniques

7. Multi-Gigabit Serial Interconnects Sample topics Backplane & cable interconnect Backplane & cable signal conditioning Copper vs. fiber trade-offs Design verification & validation Ethernet architectures Loss & timing budgets Physical modeling & simulation Signal integrity for backplanes & cables SerDes design techniques System interconnect architecture Switch-fabric architectures 8. High-Speed Timing, Jitter and Noise Sample topics Bit-error-ratio analysis & measurement Embedded clock buses Inter-symbol interference Jitter simulation, analysis & measurement Multi-gigabit signal integrity Signal conditioning Time/frequency domain translation Timing closure 9. High-Speed Signal Processing, Equalization and Coding Sample topics Active/passive pre-emphasis & equalization Adaptive tap optimization Digital pre-emphasis & equalization Error-correction coding Eye diagram compliance testing Measurement verification Multi-level signaling Signal detection algorithms Signal modeling & measurement Simulation algorithms 10. Power Integrity and Power-Aware Design Sample topics DC-DC converter characteristics Silicon power measurement & correlation Multi-voltage and power-gating design Power supply design, dynamic response Power-aware architecting Signal/power integrity co-design Power integrity optimization Charge delivery analysis Simultaneous switching noise (SSN) suppression IR-drop analysis 11. Electromagnetic Compatibility and Interference Sample topics EMI radiation and suppression ESD compliance and testing Mixed-signal design issues Near-field coupling & crosstalk Noise characterization & containment Emissions & interference modeling Shielding & package design Signal encoding & emission reduction Differential to common-mode conversion EMI measurement: near-field scanning for far-field estimation 12. Test and Measurement Methodology Sample topics Metrology of the measurements Instrumentation performance and measurement errors Resolution & sensitivity Algorithms for accuracy & resolution improvement Calibration & accuracy Methods and system architecture ATE and subsystems Automatic test pattern generation Boundary scan, JTAG & I-JTAG test methods Fluctuations, noise, jitter transformation Active/passive device measurement methods Analog, mixed signal & RF testing SoC testing: memory, IP Package, connector, board testing Testing gigabit I/O Fixture de-embedding methodologies Signal integrity and fixture de-embedding 3D-solver and measure-based test fixture design methods Backplane/pin signal integrity Chip/Package/Board/System measurement methods Separation effects of decoupling, power, signal integrity Silicon characterization/de-embedding Probing & on-wafer measurements Advanced measurements & DFM Yield analysis & yield enhancement Fault modeling & failure analysis Prototyping Test coverage 13. RF and Signal Integrity Sample topics RF chip/package/board design and simulation Nonlinear RF circuit simulation with coupled chip/package/board parasitics RF module EMI/EMC Portable wireless device system signal integrity Portable wireless device receiver de-sense Portable wireless device power distribution RF system noise Digital-analog system integration Common mode radiation Intermodulation distortion, RF leakage, noise figure, DC offset in radio circuits caused by Chip/Package/Board parasitics RF and EMI system susceptibility RF and system EMC radiation Minimizing crosstalk in high speed channels 14. Business and Engineering Impacts Sample topics Business impact of engineering decisions Engineering impact of business decisions Cost vs. performance trade-offs Designing for time to market Fabless design business issues Globalization impacts Make vs. buy decision process Market constraints on design Outsourcing, legal & personnel issues Packaging selections Partner selection process & methods Product cycles & versioning Product/component costing analysis methods Reuse decision metrics Strategic and tactical balance Third-party IP business & legal models Tradeoffs due to resources Venture start-up process