Designing high-speed serial links presents new challenges that conventional signal integrity tools can’t address: multi-million bit simulations, accurately modeling broadband interconnect characteristics and modeling the equalization / clock recovery behavior of a specific semiconductor vendor’s SerDes IP. SiSoft's Quantum Channel Designer (QCD) is a dedicated, system-level design and analysis environment for 2-20 Gbps serial links. QCD incorporates the latest frequency-domain, time-domain and statistical techniques to simulate the combined behavior of the passive channel and SerDes IP . Designers capture designs graphically, then experiment with different physical layout & equalization strategies to predict how design tradeoffs affect operating margins and link Bit Error Rate (BER). Standards-based (IBIS-AMI) SerDes IP models provide the accuracy and performance required to meet the needs of serial link design.

Designing high-performance parallel interfaces requires predicting system operating margins down to the millivolt and picosecond level. Quantum-SI automates system-level timing and signal integrity analysis, computing voltage and timing margins across an entire high-speed interface. Quantum-SI automatically post-processes simulation results based on component timing specifications, including complete support for DDR2 / DDR3 analysis. Quantum-SI allows designers to perform “what-if” simulations during pre-route analysis that determine the impact of design tradeoffs on system voltage and timing margins. Automated post-route analysis allows designers to read in routed PCB databases and be running post-route simulations within minutes.Quantum-SI design kits provide complete simulation setups for popular interface standards like DDR2 / DDR3, allowing designers to enter their design-specific topologies and begin running simulations quickly.