HyperLynx offers the most complete PCB analysis tool suite for signal integrity and power integrity with the end user in mind.  HyperLynx allows designers to analyze complex SERDES interfaces, including bit error rate (BER) validation, by predicting and simulating with worst-case bit sequences specific to the channel.  It also offers designers complete timing verification and signal integrity analysis for DDR, DDR2, and DDR3 interfaces in an interface optimized for the DDR technologies.  HyperLynx Power Integrity allows designers to root-cause DC drop problems and interactively resolve issues in an easy-to-use exploratory environment.  Designers can also perform PCB decoupling analysis, including planning and optimization prior to layout, to validate that power distribution networks meet target impedances, and voltage ripple specifications are met at IC supply pins.Visit Mentor's booth #419 to see a demonstration of HyperLynx.

HyperLynx Analog provides a simplified PCB design flow leveraging one schematic for both functional analysis and PCB layout. With all analysis options (DC, AC, Transient, Worst Case, Monte Carlo, Parametric Sweeps, Noise,etc..)  included as "standard functionality" HyperLynx Analog provides the capabilities required to insure the design works the first time in addition to allowing you to anticipate your manufacturing yields due to component distribution tolerances. With EZwave for HyperLynx providing state of the art waveform display and analysis your productivity will skyrocket with "drag and drop" simplicity for your most demanding waveform calculations. HyperLynx Analog tackles the traditional SPICE capacity, run time performance and simulation convergence obstacles so that you may focus your efforts on PCB design. HyperLynx Analog is also the only PCB functional simulation technology available that is upgradeable to include true mixed-language, mixed signal design support with VHDL, Verilog, VHDL-AMS and Verilog-A(MS). Drop by booth  419 for a demonstration of HyperLynx Analog so that you may escape the "prototype & iterate blues". Visit Mentor's booth  #419  to see a demonstration of HyperLynx Analog.

From capturing the design intent then moving through to design verification CES provides an intuitive environment for exploring and define constraints. CES is tightly integrated with all aspects of the flow providing a data conduit between the different disciplines such as systems designer, FPGA designer, board designer and signal integrity engineer. In this multi-disciplined environment CES plays a major role in reducing the design cycle time with its unique ability to allow multiple designers to enter the constraints simultaneously on the same data - each designer can immediately see the new data and changes made by their peers, no time spent managing multiple data files. Visit Mentor's booth #419  to see a demonstration of CES.

Mentor’s RF design solution provides an industry-first integration of Package/PCB design and RF circuit design. Designers can enter schematics, perform all layout tasks, and prepare data for manufacturing when designing with RF circuits. Additionally, this solution provides dynamic integration and library / database synchronization with the Agilent ADS and AWR tools, resulting in a complete solution of RF circuit design, Package design, PCB design, and system simulation.  Visit Mentor's booth #419  to see a demonstration of RF Design Solution.

Mentor’s Advanced Packaging solution is a correct-by-design system for chip packaging and chip on board using a true, 3D solution for wire bonding and cavities. Designers can implement advanced wire bonding and board cavities with high confidence in first-turn success while maintaining high yields. Unlike the competition, our solution provides integrated real-time 3D DRC as opposed to after-the-fact in a 3D viewer and our unique 3 plane 3D parametric wire bond model can better mimic the real life wire bonds and deliver tighter bond patterns than traditional technology. Visit Mentor's booth #419 to see a demonstration of Advanced Packaging.

HyperLynx offers the most complete PCB analysis tool suite for signal integrity and power integrity with the end user in mind.  HyperLynx allows designers to analyze complex SERDES interfaces, including bit error rate (BER) validation, by predicting and simulating with worst-case bit sequences specific to the channel.  It also offers designers complete timing verification and signal integrity analysis for DDR, DDR2, and DDR3 interfaces in an interface optimized for the DDR technologies.  HyperLynx Power Integrity allows designers to root-cause DC drop problems and interactively resolve issues in an easy-to-use exploratory environment.  Designers can also perform PCB decoupling analysis, including planning and optimization prior to layout, to validate that power distribution networks meet target impedances, and voltage ripple specifications are met at IC supply pins. Visit Mentor's booth #419  to see a demonstration of HyperLynx.

In the past, FPGAs were typically low density and low performance used primarily as "glue" logic to piece together a system. Today, FPGAs are high density, high performance components used to implement major system functionality. Since the current trend is to use multiple FPGAs on a PCB, the need to streamline the FPGA to PCB process is critical to system design success.  New FPGA/PCB concurrent design processes and tools significantly improve system performance, product costs, and designer productivity. Visit booth 419 to learn more.Visit Mentor's booth   #419 to see a demonstration of I/O Designer.