Design of high speed multi-gigabit serial links has reached an analysis roadblock at speeds over 5 gigabit-per-second. This is largely due to the inability to accurately model the complex dynamic equalization that takes place inside the transceivers. Cadence supports the new algorithmic modeling interface (AMI) standard recently adopted by IBIS 5.0. This new capability will allow SerDes vendors to create an industry standard model for their complex transceivers. The advantage to systems companies is vendor interoperability and shorter design cycles due to faster, more accurate simulations within the design environment.

Power delivery network (PDN) analysis is a required piece of high frequency PCB and package design. Allegro tools enable a methodology for validating power delivery by analyzing impedance of the PDN. They also provide for techniques for validating power stability while signals are switching. The methodology includes being able to identify PDN problems, modify the design, and reanalyze without having to translate the design data.

The capacity and complexity of analog designs increase exponentially to meet the stringent requirements of modern standards and the limitations of advanced process nodes. Analog/RF and mixed signal simulation has become a multi-week task. Settling for less accurate verification techniques compromises Silicon quality and leads to multiple re-spins. Virtuoso Accelerated Parallel Simulator bridges the analog block verification gap with significant single-thread and multi-thread performance and dramatic improvement to capacity. The new simulator delivers equivalent accuracy and identical use model to Virtuoso Spectre Simulator, the golden reference for analog simulation. The Virtuoso Accelerated Parallel Simulator is part of the Virtuoso Multi-Mode Simulation suite.