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Booth #941

www.atrenta.com

Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 140 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. Atrenta, Right from the Start!

Technologies on Display:
  • SpyGlass®-Power
    IC Design Tools

    The SpyGlass®-Power solution is a comprehensive solution to guide low-power design and help manage multiple power and voltage domains. Users can tune their designs for power consumption and efficiency at the register transfer level (RTL). The SpyGlass-Power solution provides early information about power consumption at RTL, and provides guidance where power can be reduced. The SpyGlass-Power solution not only detects, but can also automatically fix, key power management issues.

    The advantages are significant. Traditional approaches address power analysis and optimization at the gate level, making changes difficult and costly and complicating verification. The SpyGlass-Power solution, by contrast, enables users to tune power characteristics during RTL creation, when the design impact is greatest and the cost of modifications lowest. It can significantly shorten development cycles, reduce costs and improve the power characteristics of the finished product.

  • SpyGlass®
    IC Design Tools

    Atrenta’s SpyGlass® platform provides a powerful mix of proven design analysis tools with broad applicability throughout the SoC flow. The SpyGlass platform includes a proven tool suite for linting, CDC verification, DFT & constraints analysis and power management applicable at RTL as well as the gate level.

    SpyGlass enables Early Design Closure® - providing visibility to design risks earlier than ever and at higher design abstractions than ever. During the course of chip development, design goals evolve and get refined from the initial RTL development phase to the final SoC implementation phase. The SpyGlass platform offers a consistent solution that can be used effectively at each stage of the design evolution to achieve the respective design goals. The use of the right SpyGlass tools at the right stage of design development helps design teams achieve a predictable & repeatable methodology for Early Design Closure.

  • 1Team
    IC Design Tools

    Design Capture & Exploration- 1Team® Product Family

    1Team-Genesis - Architecture capture and chip assembly

    1Team-Implement - Model physical effects at RTL

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