DesignCon 2009: Authors

Information for Authors

Here, you will find information for speakers, room assignments, speaker registration, and a wealth of other information to make your experience at the DesignCon 2009 as productive as possible.

Please check back often as information will be updated on a regular basis.

Paper Preparation Instructions for Microsoft Word

Information in this section includes the following:

- IEC Contacts
- Room Setup
- On-Site Speaker Preparation Room
- Paper Deadline
- Presentation Guidelines
- Day of Presentation
- Session Format
- Registration and On-Site Check-In
- Speaker Substitutions
- Paper Award Info
- Room Locations

IEC Contacts

Christine Paplaczyk Exhibit and Sponsorship Opportunities Phone: +1-312-559-4616 cpaplaczyk@iec.org	Don Flood Operations Phone: +1-312-559-3322 dflood@iec.org	Barry Sullivan Content Development Phone: +1-312-559-3302 bsullivan@iec.org
Kate Lyons Speaking Opportunities Phone: +1-312-559-3326 klyons@iec.org	Lynne Bobak Event Marketing Phone: +1-312-559-3862 lbobak@iec.org	Katie Post Media Relations and Public Relations Phone: +1-312-559-3658 kpost@iec.org
Michelle Klein Exhibitor Marketing Phone: +1-312-559-3861 mklein@iec.org	Katie Post Associate Sponsor Relations Phone: +1-312-559-3658 kpost@iec.org

Room Setup Session rooms are equipped with the following:

LCD projector
Cabling
Screen
Microphone at speaker head table and podium
Tent cards with names of speakers placed at speaker seating
Head table for all speakers placed at the front of the room

If you have special AV needs in addition to those included in the standard room setup, please contact Andrea Scrementi at ascrementi@iec.org.

Please note: Laptop computers are not provided in the rooms.

On-Site Speaker Preparation Room A dedicated speaker preparation room will be available to all speakers. Room TBD. Speakers are welcome to use the speaker preparation room for on-site preparation meetings with their panelists.

Paper Deadline Deadline: All papers are due by Friday, November 21, 2008.

Papers should be prepared using the formatting guidelines and sent to Andrea Scrementi at ascrementi@iec.org.

Formatting guidelines PDF

Formatting guidelines MS Word

Presentation Guidelines The following are some helpful tips in regard to producing your presentation:

Presentations are to be noncommercial.
The IEC does not have a PowerPoint template; feel free to use your own.
Avoid too much content on one slide, as attendee feedback has voiced negative comments with regard to this.
Keep in mind that presentations are meant to provide the same information contained in the paper itself but in a condensed and visually acceptable format.
We encourage authors to send their presentations for posting on the DesignCon Web site. Please send to ascrementi@iec.org by Friday, January 9, 2009.

Day of Presentation The day of your presentation, please bring your laptop computer, as laptops are not provided in session rooms. We suggest loading all presentations on one laptop for easy transition from one speaker to the next.

Session Format

Paper sessions are 40 minutes long.
Speakers should prepare 30-minute presentations, leaving 10 minutes for questions and discussion.

Registration and On-Site Check-In Registration: Speakers and authors for DesignCon 2009 should register at
www.designcon.com/2009/register/speaker_reg.asp to receive complimentary registration for the full four-day program.

On-Site Check-In: Once you arrive at the Santa Clara Convention Center, speakers are asked to check in at the DesignCon registration desk to pick up name badges and other credentials.

Speaker Substitutions Inform IEC staff Andrea Scrementi and/or Barry Sullivan of any speaker substitutions.

If substitutions arise at the event, go to an Advance Registration counter and let the staff member attending the desk know who you are replacing.

Paper Award Info DesignCon Paper Awards recognize outstanding contributions to the educational goals of the DesignCon program. Papers are judged both on the merits of the written document and on the quality of their presentation at DesignCon events.

The awards serve to acknowledge the authors who receive them as leading practitioners in semiconductor and electronic design. The awards also provide incentive to authors to produce high-quality DesignCon papers and present them in a lucid and compelling manner.

Paper Review

The first step of the selection process is a review of the full-length papers accepted for the DesignCon 2008 technical program. Members of the DesignCon 2008 Technical Program Committee will receive the full-length papers for the tracks they reviewed. They will send their choices for the top papers in the track to Barry Sullivan, DesignCon program director. Finalists for each track will be selected based on the votes from the reviewers.

Papers are judged along the following dimensions, listed in order of importance:

1. Quality—An award-quality paper should be well organized and easily understood. This is a straightforward area to judge, especially on a relative basis.

2. Relevance—The paper should be highly relevant to the interests of the DesignCon audience and the track topic in particular.

3. Impact—Award papers should make a substantial contribution to the educational mission of DesignCon. Papers reporting on important results, methodologies, or case studies of special significance should be recognized.

4. Originality—This area requires special note. Keeping in mind the goal of providing a high-quality educational program for practicing engineers, it is easy to see that a report on a new design methodology or a case study for an innovative design has great educational value. However, an outstanding paper on a "classical" topic can be an award candidate, and papers of this sort should also be viewed favorably.

5. Commercial content—Another area deserving special mention. It is acceptable to use a product in a design case study or as a proof of concept for a design methodology, and many of the papers the DesignCon audience views most favorably do just that. However, we also know that the audience responds most negatively to anything that comes across as a product pitch. A good case study that uses a real product in an appropriate manner to demonstrate feasibility or illustrate a concept should be considered favorably.

Judging Presentations

Effective presentations add significantly to the educational value of the DesignCon technical program. While selection as a finalist for a DesignCon Paper Award is a notable achievement in itself, award winners will be chosen from among the finalists based on the quality of their presentations. The same dimensions for evaluation of the written papers—quality, relevance, originality, and commercial content—apply here as well, although quality will be the primary criterion. Judges are recruited from the DesignCon 2008 Technical Program Committee to ensure adequate coverage of the award areas listed above.

Room Locations

Monday, February 4
TIME	SESSION	LOCATION
9:00 – 12:00	TF-MA1 \| Tutorial Practical Techniques for Understanding, Modeling, and Efficiently Suppressing the Noise Coupling through Chip, Package, and PCB in Mixed-Signal Integrated Circuits and Systems-on-Chip	Ballroom E
	TF-MA2 \| Tutorial Signal Integrity Measurement Methods and Practices	Ballroom F
	TF-MA3 \| Tutorial Impact of Power Management Techniques on SoC Design and Verification	Ballroom G
	TF-MA4 \| Tutorial Fixturing and Calibration Techniques for Obtaining Wide Bandwidth Measured Data for Time Domain Simulations and Measurement-Based Modeling	Ballroom H
	TF-MA5 \| Tutorial Ensuring Functional Closure of a Complex SoC Through Verification Planning, Implementation and Execution	Room 209/210
12:30 – 1:00	Monday Keynote Luncheon	Great America Ballroom JK
1:30 – 4:30	TF-MP1 \| Tutorial CoReUse/QCore - Industry�s First Design Reuse Methodology with Compliance Checking Tool	Ballroom E
	TF-MP2 \| Tutorial Advances in Gigabit Channel Measurement-Based Characterization and Simulation	Ballroom F
	TF-MP3 \| Tutorial Design and Verification for High-Speed I/Os at Multiple to >10 Gbps with Jitter and Signal Integrity Optimization	Ballroom G
	TF-MP4 \| Tutorial Understanding Grounding Concepts in EM Simulators — What the Signal	Ballroom H
	TF-MP6 \| Tutorial Low Power Flows and Formats: From ESL to Implementation	Room 203/204
4:45 – 6:00	Technical Panel How Can Semiconductor Designers Meet High Performance/Low Power Requirements for Customers by Providing Greater Choice at Advanced Technology Nodes?	Ballroom E
	Technical Panel The Case of the Closing Eye - Addressing the Industry's Next-Gen Serial Data Design Validation Challenges	Ballroom F & G
	Technical Panel Power Distribution Planes: to Split or Not to Split?	Ballroom H
Tuesday, February 3
TIME	SESSION	LOCATION
8:30 – 9:10	3-TA1 Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP	Ballroom H
	6-TA1 Analysis of cross talk between signals routed over discontinuous reference plane	Great America Ballroom J
	7-TA1 Optimizing Connector Models for Signal Integrity Use	Great America Ballroom K
	8-TA1 The use of Optimization in Signal Integrity performance Centric High Speed Digital Design Flows	Ballroom E
	10-TA1 FPGA/ASIC Pre-driver PDN SSN and Its Impact on SSJ	Ballroom F
	13-TA1 Active Cancellation of Noise Coupling in Mixed-Signal Integrated Circuits: Methodology, Design Examples, and Experimental Results	Ballroom G
8:30 – 10:00	Business Forum Panel Design This! New Strategies for New Devices	Room 203/204
	3-TA2 Configurable DAC for Mixed-Signal SoC Integration, with Maximum Design re-usability	Ballroom H
	6-TA2 Incorporating SSN Analysis in Constraint-Based System Design	Great America Ballroom J
	7-TA2 Practical Analysis of Backplane Vias for 5 Gbps and Above	Great America Ballroom K
	8-TA2 Quantifying Crosstalk Induced Jitter in Multi-lane Serial Data Systems	Ballroom E
	10-TA2 A novel methodology to handle the layout constraints for designing an optimal Power Delivery Network	Ballroom F
	13-TA2 Fully Analytical Methodology for Fast End-to-End Link Analysis on Complex Printed Circuit Boards including Signal and Power Integrity Effects	Ballroom G
	14-TA2 Web 2.0 Tools for Engineers	Room 209/210
10:10 – 10:50	2-TA3 High-Speed SerDes Design and Verification using an EDA-based Silicon-Accurate Behavioral Modeling and Simulation Methodology	Room 209/210
	3-TA3 Intellectual Property - Fraud Protection	Ballroom H
	4-TA3 Worst Case Switching Pattern for Core Noise Analysis	Great America Ballroom J
	7-TA3 Performance Calibration of High Speed Serial Links	Great America Ballroom K
	8-TA3 Analysis of Random Noise and the Effect of Band-Limited Noise on Stressed-Eye Receiver Tolerance Tests	Ballroom E
	13-TA3 De-embed Probe with New Switched Load Tip Technology	Ballroom G
10:10 – 11:40	Business Forum Panel Embracing a New Paradigm: EDA Tools and IP as Solutions	Room 203/204
11:00 – 11:40	2-TA4 Multivariate Multi-objective Analog Design Optimization using High-Level Analog Testbenches	Room 209/210
	3-TA4 Towards Harnessing the True Potential of IP Reuse	Ballroom H
	4-TA4 System IO Planning and Design Feasibility ? Challenges and Solutions	Great America Ballroom J
	7-TA4 A Signal Integrity Comparison of 25 Gbps Backplane Systems Using Varying High-Density Connector Performance Levels	Great America Ballroom K
	8-TA4 A New Physical Mechanism-Based Jitter Classification Method and Its Applications	Ballroom E
	10-TA4 Power-gating design tradeoffs and considerations for production low-power designs	Ballroom F
	13-TA4 Verify Your Signal Integrity Margins: De-Embedding of Fixtures and Probing in a Real-Time Digital Oscilloscope	Ballroom G
	UNIV Design challenges for Next Generation High Speed Ethernet; 40 and 100GbE	Room 212
11:50 – 12:30	Tuesday Keynote Address	Great America Ballroom JK
2:00 – 2:40	1-TP1 A Case Study: Critical Area and Critical Feature Analysis of Production 90nm Designs at LSI Corporation	Room 209/210
	3-TP1 C++ IP Design and Reuse	Ballroom H
	5-TP1 Common Mode Effects on Multigigabit-per-second Interconnects	Ballroom J
	6-TP1 Analyzing Signal and Power Integrity Limitations for Mobile Memory Systems in PoP Environments	Great America Ballroom K
	8-TP1 Comparison of BER Estimation Methods which Account for Crosstalk	Ballroom E
	11-TP1 The Application of High Speed Serial Interfaces to Highly Sensitive EMI Applications	Ballroom F
	12-TP1 Guidelines for Multiport and Mixed-Mode S-Parameter Measurements in High-Speed Interconnection Design	Ballroom G
2:00 – 3:30	Business Forum Panel Collaboration across the Changing Design Chain	Room 203/204
2:50 – 3:30	1-TP2 Equation-Based DRC: A Novel Approach to Resolving Complex nm Design Issues	Room 209/210
	3-TP2 Skeleton, an Approach to Maximize Reuse across Multiple Product Families	Ballroom H
	5-TP2 A Simple Via Experiment	Great America Ballroom J
	8-TP2 Noise and Jitter Analysis for PLL-based Frequency Synthesizer	Ballroom E
	11-TP2 Control of Electro-Magnetic Radiation from Integrated Circuit Heat sinks	Ballroom F
	12-TP2 Contactless vector network analysis - A new approach for S-Parameter measurements	Ballroom G
3:45 – 5:00	Technical Panel Selecting IP in a Complex Design Environment	Ballroom F
	Technical Panel Multi-die Chip/Package Co-design for SiP Applications	Ballroom G
	Technical Panel High-speed channel designs - Challenges and solutions	Ballroom H
	Business Forum Panel New Media/New Marketing: Using On-Line Media to Gain a Competitive Edge	Room 203/204
Wednesday, February 4
TIME	SESSION	LOCATION
8:45 – 9:25	1-WA1 A Self-Adaptable Slew Rate Control Variable Power Supply Output Buffer for Embedded Microcontroller	Room 209/210
	4-WA1 Feasibility of Multi-Gigabit Memory Interface in LQFP Packages	Ballroom H
	6-WA1 A Study of Transmission Technology to Support 25 Gbps Serial Signaling for Parallel Architectures in Multi-Board Coplanar PCB Systems	Great America Ballroom J
	7-WA1 Crosstalk in High-Speed Via Pin Fields Including the Impact of Power Distribution Structures	Great America Ballroom K
	10-WA1 Prediction and Measurement of Supply Noise Induced Jitter in High-Speed I/O Interfaces	Ballroom E
	12-WA1 Measurement-Assisted Electromagnetic Extraction of Interconnect Parameters on Low-Cost FR�4 boards for 6�20 Gbps Applications	Ballroom G
	13-WA1 Crosstalk Amplification by Resonance	Ballroom F
	14-WA1 Modeling Design Services for Improving Service Delivery Effectiveness	Room 203/204
9:20 – 10:00	1-WA2 Design Space Exploration for High-Performance Signal-Processing Hardware Using ESL Design Methodology	Room 209/210
9:40 – 10:20	4-WA2 Broadband Methodology for Power Distribution System Analysis of Chip, Package, and Board for High-Speed IO Design	Ballroom H
	6_WA2 Clock Jitter Reduction in High Speed Interfaces	Great America Ballroom J
	7-WA2 Methodology of Characterizing Chip-to-Chip Serial Interconnects with AC Coupling Capacitors	Great America Ballroom K
	9_WA2 Adaptive Transmit Equalization for Hybrid Optical-Electrical Links Operating at Speeds up to 17.0 GB	Ballroom E
	12-WA2 VNA Characterization of Cable Assemblies for Supercomputer Applications	Ballroom G
	13_WA2 40 Gbps Pre-Emphasized Serializer, Equalizer, and CDR CMOS Circuit Design with Full Channel Simulation	Ballroom F
	14-WA2 Business considerations for systems with RAM-based FPGA configuration	Room 203/204
10:15 – 10:55	1-WA3 Analog Chip-Level Behavioral Modeling Using SVM Kernel-Based Data Mining Techniques	Room 209/210
	4-WA3 Design Optimization of High Speed Digital Systems	Ballroom H
	5-WA3 Bounding the Glass Weave Effect through Simulation	Great America Ballroom J
	7-WA3 How Long is too Long? A Via Stub Electrical Performance Study	Great America Ballroom K
	9-WA3 Pseudo-Differential Vector Signaling for Noise Reduction in Single-ended Signaling Systems	Ballroom E
	10-WA3 Examining the impact of split planes on signal and power integrity	Ballroom F
	12-WA3 Characterizing Non-Standard Impedance Channels with 50 Ohm Instruments	Ballroom G
11:05 – 11:45	1-WA4 Method and Apparatus of Continuous PLL Adaptation to Variable Reference Input Frequency	Room 209/210
	4-WA4 Time and Frequency Analysis of Signal-Noise as a Function of Power-Noise and vice versa	Ballroom H
	5-WA4 Power Integrity Effects of High Density Interconnect (HDI)	Great America Ballroom J
	7-WA4 BER Performances for High-Speed Serial Link System Estimated by using Quasi-Analytical Method	Great America Ballroom K
	9-WA4 New Methods of Measuring the Performance of Equalized Serial Data Links and Correlation of Performance Measures across the Design Flow, from Simulation to Measurement, and Final BER Tests	Ballroom E
	11-WA4 Common Mode EMI From Disk Drive Gigabit Serial Interfaces	Ballroom F
	12-WA4 Application of Launch Point Extrapolation Technique to Measure Characteristic Impedance of High-Frequency Cables with TDR	Ballroom G
2:00 – 2:40	2-WP1 Formal Verification of Multi-level Model System using UPF	Room 209/210
	4-WP1 SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity	Ballroom H
	5-WP1 Achieving 100 Percent PCB/Substrate-Level ESD Protection to 30 KV Using VSD� Nano-Composites	Great America Ballroom J
	6-WP1 The Design and Signal Integrity Analysis of a TB/sec Memory System	Great America Ballroom K
	9-WP1 Statistical Analog Front End and Decision Feedback Equalization	Ballroom E
	10-WP1 An Efficient Time-Domain Method for the Analysis and Design of the Decoupling Networks in High-Speed	Ballroom F
	12-WP1 Platform Validation using Intel? IBIST	Ballroom G
	Business Forum Panel Do It Right or Do It Over? Signal Integrity Engineer in the Era of Highly Compressed Project Schedules	Room 203/204
2:50 – 3:30	2-WP2 Using a Memory Access Pattern Test Suite to Predict System Performance	Room 209/210
	4-WP2 The Effects of Chip and Board Behavior on Package-Centric, System-Aware Power Delivery Design	Room 209/210
	5-WP2 Advances in Plating Technology	Great America Ballroom J
	7-WP2 Interconnect Design Optimization and Characterization for Advanced High-Speed Backplane Channel Links	Great America Ballroom K
	9-WP2 40/100 Gbps Transmission over Copper: Myths and Realities	Ballroom E
	11-WP2 EMI from Multi-Gigabit SerDes Differential Pairs	Ballroom F
	12-WP2 Characterizing Jitter Transfer in Clock Circuits	Ballroom G
3:45 – 5:00	Business Forum Panel Globalization of Product Engineering	Room 203/204
	Technical Panel Getting What You Pay for at 32 nm	Ballroom F
	Technical Panel Power-Aware Verification: Is It a Front-End or a Back-End Issue?	Ballroom G
	Technical Panel Measurements versus Simulations: Electrical Modeling at Future Data Rates and Physical Dimensions	Ballroom H
Thursday, February 5
TIME	SESSION	LOCATION
9:00 – 9:40	10-TH1 Voltage Regulator Module and Power Distribution Network Optimization	Ballroom G
	12-TH1 Characterization and Focus Calibration of ATE Systems for High-Speed Digital Applications	Ballroom H
	13-TH1 Utilizing Electronic Dispersion Compensation (EDC) and embedded waveform viewing technologies in next generation backplanes	Ballroom E
9:50 – 10:30	7-TH2 New Serial Link Simulation Process, 6 Gbps SAS Case Study	Ballroom F
	10-TH2 PCB Power Delivery Optimizations for the Cost-Driven Era	Ballroom G
	12-TH2 A Comparison of Fixture Removal Methods for Characterization of Differential PCB Channels	Ballroom H
	13-TH2 Noise Injection for Design Analysis and Debugging	Ballroom E
10:40 – 11:20	10-TH3 Switching Voltage Regulator Noise Coupling Analysis for Printed Circuit Board Systems	Ballroom G
	12-TH3 High-Performance and Cost-Effective Time-Domain TRL (t-TRL) Calibration Technique for High-Speed PWC Characterization and Qualification	Ballroom H
	13-TH3 Leveraging Probe De-Embedding Technique for Multi-Gigabit FPGA Package Characterization	Ballroom E

Attendees:

Exhibitors:

Authors:

Press: