DesignCon 2009: Attendees: Schedule by Track

DesignCon 2009 Schedule by Track

By Date | By Track

All

Keynotes

Business Forums

Technical Panels

Tutorials

Technology Exhibition

Track 1 | Chip-Level System Design

Track 2 | Functional Verification

Track 3 | IP Reuse and Integration

Track 4 | System Co-Design: Chip/Package/Board

Track 5 | PCB and Passive Component Technology

Track 6 | High-Speed Parallel Interface Design

Track 7 | Multi-Gigabit Serial Interconnects

Track 8 | High-Speed Timing, Jitter, and Noise

Track 9 | High-Speed Signal Processing, Equalization, and Coding

Track 10 | Power Integrity and Power-Aware Design

Track 11 | Electromagnetic Compatibility and Interference

Track 12 | Test and Measurement Methodology

Track 13 | RF and Signal Integrity

Track 14 | Business and Engineering Impacts

Keynotes

Monday, February 2

Noon – 1:00	Monday Keynote Luncheon
	Speaker: Mark Gogolewski Chief Technology Officer, Engineering Department Denali Software
Tuesday, February 3
Noon – 12:30 pm	Tuesday Keynote Address
	Speaker: Wally Rhines Chairman and Chief Executive Officer Mentor Graphics
Wednesday, February 4
Noon – 12:30 pm	Wednesday Keynote Address
	Speaker: Dr. Paolo A. Gargini Director of Technology Strategy Intel Corporation

Business Forums

Tuesday, February 3

8:30 am – 10:00 am	Design This! New Strategies for New Devices
	Chairperson: Dylan McGrath Senior Editor EE Times
10:15 am – 11:45 am	Embracing a New Paradigm: EDA Tools and IP as Solutions Enablers
	Chairperson: Bill Martin IP Interest Group Chair, Global Semiconductor Alliance (GSA) General Manager, Verification IP Mentor Graphics
2:00 pm – 3:30 pm	Collaboration across the Changing Design Chain
	Chairperson: Dian Yang Senior Vice President, Product Management Apache Design Solutions
3:45 pm – 5:00 pm	New Media/New Marketing: Using On-Line Media to Gain a Competitive Edge
	Chairperson: Rhonda McGee Director of Research, Boston Reed Business Information
Wednesday, February 4
2:00 pm – 3:30 pm	Do It Right or Do It Over? Signal Integrity Engineer in the Era of Highly Compressed Project Schedules
	Chairperson: Paul Rako Technical Editor, EDN Magazine Reed Business Information
3:45 pm – 5:00 pm	Globalization of Product Engineering

Technical Panels

Monday, February 2

4:45 pm – 6:00 pm	How Can Semiconductor Designers Meet High Performance/Low Power Requirements for Customers by Providing Greater Choice at Advanced Technology Nodes?
	Chairperson: Tom Quan Deputy Director, Design Service Marketing TSMC
	The Case of the Closing Eye — Addressing the Industry�s Next-Gen Serial Data Design Validation Challenges
	Chairperson: Chris Loberg Senior Manager, Business Instruments Tektronix
	Power Distribution Planes: To Split or Not to Split?
	Chairperson: Istvan Novak Distinguished Engineer, SPARC Volume Servers Sun Microsystems
Tuesday, February 3
3:45 pm – 5:00 pm	Selecting IP in a Complex Design Environment
	Chairperson: Raghavan Menon Director of Engineering, ASIP Virage Logic
	Multi-Die Chip/Package Co-Design for SiP Applications
	Chairperson: An-Yu Kuo Chief Architect Apache Design Solutions
	High-Speed Channel Designs — Challenges and Solutions
	Chairperson: Moises Cases Distinguished Engineer, STG IBM
Wednesday, February 4
3:45 pm – 5:00 pm	Getting What You Pay for at 32 nm
	Chairperson: Joseph Sawicki Vice President and General Manager, Design-to-Silicon Division Mentor Graphics
	Power-Aware Verification: Is It a Front-End or a Back-End Issue?
	Chairperson: Bhanu Kapoor Consultant/Owner Mimasic
	Measurements versus Simulations: Electrical Modeling at Future Data Rates and Physical Dimensions
	Chairperson: Brett Grossman Senior Staff SI Engineer, Sort Test Technology Development Intel

Tutorials

Monday, February 2

9:00 am - Noon	TF-MA1 \| Tutorial Practical Techniques for Understanding, Modeling, and Efficiently Suppressing the Noise Coupling through Chip, Package, and PCB in Mixed-Signal Integrated Circuits and Systems-on-Chip
	TF-MA2 \| Tutorial Signal Integrity Measurement Methods and Practices
	TF-MA3 \| Tutorial Impact of Power Management Techniques on SoC Design and Verification
	TF-MA4 \| Tutorial Fixturing and Calibration Techniques for Obtaining Wide Bandwidth Measured Data for Time Domain Simulations and Measurement-Based Modeling
	TF-MA5 \| Tutorial Ensuring Functional Closure of a Complex SoC Through Verification Planning, Implementation and Execution
1:30 pm - 4:30 pm	TF-MP1 \| Tutorial CoReUse/QCore - Industries First Design Reuse Methodology with Compliance Checking Tool
	TF-MP2 \| Tutorial Advances in Gigabit Channel Measurement-Based Characterization and Simulation
	TF-MP3 \| Tutorial Design and Verification for High-Speed I/Os at Multiple to >10 Gbps with Jitter and Signal Integrity Optimization
	TF-MP4 \| Tutorial Understanding Grounding Concepts in EM Simulators - What the Signal Integrity Engineer Needs to Know
	TF-MP5 \| Tutorial Multicore and Virtualization Key Enablers for Next-Generation Network Architecture
	TF-MP6 \| Tutorial Low Power Flows and Formats: From ESL to Implementation

Technology Exhibition

Tuesday, February 3

12:30 pm – 2:00 pm	Lunch Served on the Exhibit Floor
5:00 pm – 6:30 pm	Exhibits and Reception
Wednesday, February 4
12:30 pm – 2:00 pm	Lunch and Exhibits
5:00 pm – 6:30 pm	Exhibits and Reception

Track 1 | Chip-Level System Design

Tuesday, February 3

2:00 pm - 2:40 pm	1-TP1 A Case Study: Critical Area and Critical Feature Analysis of Production 90 nm Designs at LSI Corporation
2:50 pm – 3:30 pm	1-TP2 Equation-Based DRC: A Novel Approach to Resolving Complex nm Design Issues
Wednesday, February 4
8:30 am – 9:10 am	1-WA1 A Self-Adaptable, Slew-Rate Control, Variable Power Supply Output Buffer for Embedded Microcontroller Applications with EMI Improvement Using Geometric-Load-Slew Factor Approach
9:20 am – 10:00 am	1-WA2 Design Space Exploration for High-Performance Signal-Processing Hardware Using ESL Design Methodology
10:15 am – 10:55 am	1-WA3 Analog Chip-Level Behavioral Modeling Using SVM Kernel-Based Data Mining Techniques
11:05 am – 11:45 am	1-WA4 Method and Apparatus of Continuous PLL Adaptation to Variable Reference Input Frequency

Track 2 | Functional Verification

Tuesday, February 3

10:15 am – 10:55 am	2-TA3 High-Speed SerDes Design and Verification using an EDA-based Silicon-Accurate Behavioral Modeling and Simulation Methodology
11:05 am – 11:45 am	2-TA4 Multivariate Multi-Objective Analog Design Optimization Using High-Level Analog Test Benches
Wednesday, February 4
2:00 pm – 2:40 pm	2-WP1 Formal Verification of Multi-Level Model System Using UPF
2:50 pm – 3:30 pm	2-WP2 Using a Memory Access Pattern Test Suite to Predict System Performance

Track 3 | IP Re-Use and Integration

Tuesday, February 3

8:30 am – 9:10 am	3-TA1 Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP
9:20 am – 10:00 am	3-TA2 Configurable DAC for Mixed-Signal SoC Integration, with Maximum Design Reusability
10:15 am – 10:55 am	3-TA3 Intellectual Property — Fraud Protection
11:05 am – 11:45 am	3-TA4 Toward Harnessing the True Potential of IP Reuse
2:00 pm – 2:40 pm	3-TP1 C++ IP Design and Reuse
2:50 pm – 3:30 pm	3-TP2 Skeleton, an Approach to Maximize Reuse across Multiple Product Families

Track 4 | System Co-Design: Chip/Package/Board

Tuesday, February 3

10:15 am – 10:55 am	4-TA3 Worst-Case Switching Pattern for Core Noise Analysis
11:05 am – 11:45 am	4-TA4 System IO Planning and Design Feasibility — Challenges and Solutions
Wednesday, February 4
8:30 am – 9:10 am	4-WA1 Feasibility of Multi-Gigabit Memory Interface in LQFP Packages
9:20 am – 10:00 am	4-WA2 Broadband Methodology for Power Distribution System Analysis of Chip, Package, and Board for High-Speed IO Design
10:15 am – 10:55 am	4-WA3 Design Optimization of High-Speed Digital Systems
11:05 am – 11:45 am	4-WA4 Time and Frequency Analysis of Signal Noise as a Function of Power Noise and Vice Versa of a Microcontroller (�C) Plus Its Packaging (LQFP+PCB)
2:00 pm – 2:40 pm	4-WP1 SSO Noise, Eye Margin, and Jitter Characterization for I/O Power Integrity
2:50 pm – 3:30 pm	4-WP2 The Effects of Chip and Board Behavior on Package-Centric, System-Aware Power Delivery Design

Track 5 | PCB and Passive Component Technology

Tuesday, February 3

2:00 pm – 2:40 pm	5-TP1 Common-Mode Effects on Multigigabit-per-Second Interconnects
2:50 pm – 3:30 pm	5-TP2 A Simple Via Experiment
Wednesday, February 4
10:15 am – 10:55 am	5-WA3 Bounding the Glass Weave Effect through Simulation
11:05 am – 11:45 am	5-WA4 Power Integrity Effects of High Density Interconnect (HDI)
2:00 pm – 2:40 pm	5-WP1 Achieving 100 Percent PCB/Substrate Level ESD Protection to 30 KV Using VSD™ Nano-Composites
2:50 pm – 3:30 pm	5-WP2 Advances in Plating Technology

Track 6 | High-Speed Parallel Interface Design

Tuesday, February 3

8:30 am – 9:10 am	6-TA1 Analysis of Crosstalk between Signals Routed over Discontinuous Reference Plane
9:20 am – 10:00 am	6-TA2 Incorporating SSN Analysis in Constraint-Based System Design
2:00 pm – 2:40 pm	6-TP1 Analyzing Signal and Power Integrity Limitations for Mobile Memory Systems in PoP Environments
Wednesday, February 4
8:30 am – 9:10 am	6-WA1 A Study of Transmission Technology to Support 25 Gbps Serial Signaling for Parallel Architectures in Multi-Board Coplanar PCB Systems
9:20 am – 10:00 am	6-WA2 Clock Jitter Reduction in High-Speed Interfaces
2:00 pm – 2:40 pm	6-WP1 The Design and Signal Integrity Analysis of a Tbps Memory System

Track 7 | Multi-Gigabit Serial Interconnects

Tuesday, February 3

8:30 am – 9:10 am	7-TA1 Optimizing Connector Models for Signal Integrity Use
9:20 am – 10:00 am	7-TA2 Practical Analysis of Backplane Vias for 5 Gbps and Above
10:15 am – 10:55 am	7-TA3 Performance Calibration of High-Speed Serial Links
11:05 am – 11:45 am	7-TA4 A Signal Integrity Comparison of 25 Gbps Backplane Systems Using Varying High-Density Connector Performance Levels
2:50 pm – 3:30 pm	7-TP2 Virtual Compliance Design Kit Including Optimization and Sensitivity Analysis for Serial RapidIO up to 6.25 Gbps
Wednesday, February 4
8:30 am – 9:10 am	7-WA1 Crosstalk in High-Speed Via Pin Fields Including the Impact of Power Distribution Structures
9:20 am – 10:00 am	7-WA2 Methodology of Characterizing Chip-to-Chip Serial Interconnects with AC Coupling Capacitors
10:15 am – 10:55 am	7-WA3 How Long Is Too Long? A Via Stub Electrical Performance Study
11:05 am – 11:45 am	7-WA4 BER Performances for High-Speed Serial Link System Estimated by Using Quasi-Analytical Method
2:50 pm – 3:30 pm	7-WP2 Interconnect Design Optimization and Characterization for Advanced High-Speed Backplane Channel Links
Thursday, February 5
9:50 am – 10:30 am	7-TH2 New Serial Link Simulation Process, 6 Gbps SAS Case Study
10:40 am – 11:20 am	7-TH3 Development of USB3 Interconnects � Compatible Extension into Multi-Gigabit Bandwidth Performance

Track 8 | High-Speed Timing, Jitter, and Noise

Tuesday, February 3

8:30 am – 9:10 am	8-TA1 The Use of Optimization in Signal Integrity Performance�Centric, High-Speed Digital Design Flows
9:20 am – 10:00 am	8-TA2 Quantifying Crosstalk-Induced Jitter in Multi-Lane Serial Data Systems
10:15 am – 10:55 am	8-TA3 Analysis of Random Noise and the Effect of Band-Limited Noise on Stressed-Eye Receiver Tolerance Tests
11:05 am – 11:45 am	8-TA4 A New Physical Mechanism-Based Jitter Classification Method and Its Applications
2:00 pm – 2:40 pm	8-TP1 Comparison of BER Estimation Methods That Account for Crosstalk
2:50 pm – 3:30 pm	8-TP2 Noise and Jitter Analysis for PLL�based Frequency Synthesizer

Track 9 | High-Speed Signal Processing, Equalization, and Coding

Wednesday, February 4

9:20 am – 10:00 am	9-WA2 Adaptive Transmit Equalization for Hybrid Optical-Electrical Links Operating at Speeds up to 17.0 GBd
10:15 am – 10:55 am	9-WA3 Pseudo-Differential Vector Signaling for Noise Reduction in Single-Ended Signaling Systems
11:05 am – 11:45 am	9-WA4 New Methods of Measuring the Performance of Equalized Serial Data Links and Correlation of Performance Measures across the Design Flow, from Simulation to Measurement, and Final BER Tests
2:00 pm – 2:40 pm	9-WP1 Statistical Analog Front-End and Decision Feedback Equalization
2:50 pm – 3:30 pm	9-WP2 40/100 Gbps Transmission over Copper: Myths and Realities

Track 10 | Power Integrity and Power-Aware Design

Tuesday, February 3

8:30 am – 9:10 am	10-TA1 FPGA/ASIC Pre-Driver PDN SSN and Its Impact on SSJ
9:20 am – 10:00 am	10-TA2 A Novel Methodology to Handle the Layout Constraints for Designing an Optimal Power Delivery Network
11:05 am – 11:45 am	10-TA4 Power-Gating Design Tradeoffs and Considerations for Production Low-Power Designs
Wednesday, February 4
8:30 am – 9:10 am	10-WA1 Prediction and Measurement of Supply Noise�Induced Jitter in High-Speed I/O Interfaces
10:15 am – 10:55 am	10-WA3 Impact of Split Planes on Signal and Power Integrity: A Case Study
2:00 pm – 2:40 pm	10-WP1 An Efficient Time-Domain Method for the Analysis and Design of the Decoupling Networks in High-Speed Printed Circuit Boards
Thursday, February 5
9:00 am – 9:40 am	10-TH1 Voltage Regulator Module and Power Distribution Network Optimization
9:50 am – 10:30 am	10-TH2 PCB Power Delivery Optimizations for the Cost-Driven Era
10:40 am – 11:20 am	10-TH3 Switching Voltage Regulator Noise Coupling Analysis for Printed Circuit Board Systems

Track 11 | Electromagnetic Compatibility and Interference

Tuesday, February 3

2:00 pm – 2:40 pm	11-TP1 The Application of High-Speed Serial Interfaces to Highly Sensitive EMI Applications
2:50 pm – 3:30 pm	11-TP2 Control of Electro-Magnetic Radiation from Integrated Circuit Heat Sinks
11:05 am – 11:45 am	11-WA4 Common-Mode EMI from Disk Drive Gigabit Serial Interfaces
2:50 pm – 3:30 pm	11-WP2 EMI from Multi-Gigabit SerDes Differential Pairs

Track 12 | Test and Measurement Methodology

Tuesday, February 3

2:00 pm – 2:40 pm	12-TP1 Guidelines for Multiport and Mixed-Mode S-Parameter Measurements in High-Speed Interconnection Design
2:50 pm – 3:30 pm	12-TP2 Contactless Vector Network Analysis — A New Approach for S-Parameter Measurements
Wednesday, February 4
8:30 am – 9:10 am	12-WA1 Measurement-Assisted Electromagnetic Extraction of Interconnect Parameters on Low-Cost FR-4 Boards for 6�20 Gbps Applications
9:20 am – 10:00 am	12-WA2 VNA Characterization of Cable Assemblies for Supercomputer Applications
10:15 am – 10:55 am	12-WA3 Characterizing Non-Standard Impedance Channels with 50 Ohm Instruments
11:05 am – 11:45 am	12-WA4 Application of Launch Point Extrapolation Technique to Measure Characteristic Impedance of High-Frequency Cables with TDR
2:00 pm – 2:40 pm	12-WP1 Platform Validation Using Intel® IBIST
2:50 pm – 3:30 pm	12-WP2 Characterizing Jitter Transfer in Clock Circuits
Thursday, February 5
9:00 am – 9:40 am	12-TH1 Characterization and Focus Calibration of ATE Systems for High-Speed Digital Applications
9:50 am – 10:30 am	12-TH2 A Comparison of Fixture Removal Methods for Characterization of Differential PCB Channels
10:40 am – 11:20 am	12-TH3 High-Performance and Cost-Effective Time-Domain TRL Calibration Technique for High-Speed PWC Characterization and Qualification

Track 13 | RF and Signal Integrity

Tuesday, February 3

8:30 am – 9:10 am	13-TA1 Active Cancellation of Noise Coupling in Mixed-Signal Integrated Circuits: Methodology, Design Examples, and Experimental Results
9:20 am – 10:00 am	13-TA2 Fully Analytical Methodology for Fast End-to-End Link Analysis on Complex Printed Circuit Boards including Signal and Power Integrity Effects
10:15 am – 10:55 am	13-TA3 De-Embed Probe with New Switched Load Tip Technology
11:05 am – 11:45 am	13-TA4 Verify Your Signal Integrity Margins: De-Embedding Fixtures and Probing in a Real-Time Digital Oscilloscope
Wednesday, February 4
8:30 am – 9:10 am	10-WA1 Prediction and Measurement of Supply Noise Induced Jitter in High-Speed I/O Interfaces
8:30 am – 9:10 am	13-WA1 Crosstalk Amplification by Resonance
9:20 am – 10:00 am	13-WA2 40 Gbps Pre-Emphasized Serializer, Equalizer, and CDR CMOS Circuit Design with Full Channel Simulation
Thursday, February 5
9:00 am – 9:40 am	13-TH1 Utilizing Electronic Dispersion Compensation (EDC) and Embedded Waveform Viewing Technologies in Next-Generation Backplanes
9:50 am – 10:30 am	13-TH2 Noise Injection for Design Analysis and Debugging
10:40 am – 11:20 am	13-TH3 Leveraging Probe De-Embedding Technique for Multi-Gigabit FPGA Package Characterization

Track 14 | Business and Engineering Impacts

Tuesday, February 3

9:20 am – 10:00 am

14-TA2

Web2.0 Tools for Engineers

Wednesday, February 4

8:30 am – 9:10 am	14-WA1 Modeling Design Services for Improving Service Delivery Effectiveness
9:20 am – 10:00 am	14-WA2 Business Considerations for Systems with RAM�Based FPGA configuration

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Press: