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Business Forum Panel
Do It Right or Do It Over? Signal Integrity Engineers in the Era of Highly Compressed Project Schedules
Wednesday, February 4 | 2:00 pm – 3:30 pm
Most of the timing analyses in Greg Edlund’s recent book, Timing Analysis and Simulation for SI Engineers, are technical ones, but an opening section (titled “Reflections on a Near Disaster”) proposes a controversial thesis that SI crises aren’t engineering problems, but organizational ones. Specifically, competitive pressures lead companies to commit to “non-causal” schedules that call for deliverables “yesterday” and squeeze out sufficient time for SI analysis.

As Edlund observes, “Schedule should never take precedence over product quality unless the risk of non-functional hardware is deemed acceptable.”

This panel will investigate the business issues that led to us being on this treadmill and, more importantly, business solutions that will get us off.

Chairperson
rako paul
Paul Rako
Technical Editor, EDN Magazine
Reed Business Information
Mr. Rako is a former automotive engineer and electronics consultant. He has been with EDN for three years. Mr. Rako was born in Cleveland, Ohio, and worked in Detroit before moving to Silicon Valley.
Speakers
colin warwick
Greg Edlund
Senior Engineer, Electronic Packaging and Integration Technology
IBM
Mr. Edlund has worked as a signal integrity engineer for IBM, Digital Equipment Corporation, Cray Research, and Supercomputer Systems. His new book, "Timing Analysis and Simulation for Signal Integrity Engineers," reflects his long-term interest in predicting and measuring operating margins.
Hany Fahmy
Director, System Design and Manufacturing Group
NVIDIA Corporation
Dr. Fahmy is a director at NVIDIA, dealing with the design and analysis of high-speed digital and analog interconnecting systems. Before joining NVIDIA, Mr. Fahmy worked at Intel, Micron, and TI. He has a Ph.D. from the University of Toronto and an M.Sc. and a B.Sc. from Cairo University in Egypt.
Brad Griffin
Brad Griffin
Product Marketing Director, SiP, IC Packaging, and PCB High-Speed Solutions
Cadence Design Systems
Mr. Griffin is product marketing director, SiP, IC Packaging, and PCB High-Speed Solutions, of Cadence Design Systems PCB and IC Packaging User Segment. He has over 17 years of experience in EDA technologies that enable the design of integrated circuit packaging and printed circuit board systems. Mr. Griffin is a graduate of Arizona State University.
larry lerner
Larry Lerner
Senior Manager, R&D
Agilent Technologies
Mr. Lerner is the senior manager responsible for all product development at EEsof. He is also responsible for EEsof’s Signal Integrity strategy.
larry williams
Lawrence Williams
Director, Business Development
Ansoft LLC
Dr. Williams builds strategic relationships with Ansoft customers and business partners. He is responsible for the direction of products for microwave, wireless, and high-speed electronic component design. He has more than 19 years of experience in electromagnetics and communications engineering.
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