Yu Zhu, Senior Engineering Manager, SpectreRF, CIC, Cadence Design Systems
Jianwei Sun, Member of Consulting Staff, Cadence Design Systems
Andrew Li, Staff Product Engineer, Cadence Design Systems
Dan Feng, Senior Architect, Cadence Design Systems
Helene Thibieroz, Staff Support Engineer, Cadence Design Systems

In this article, we present a noise-aware PLL simulation flow. In the flow, we provide a test bench for each PLL building block, such as VCO, PFD/CP, and FD, where their voltage-domain models with noise or jitter information are extracted to capture their dominant behaviors. The models are used in the top-level PLL simulation to identify key PLL characteristics such as noise, jitter, locking settle time, and power supply and substrate interference effects. The flow is tested on an integer-N and fractional-N PLL. The results and performance are compared with those from transistor-level transient analysis.