Schedule
7-TA3
Performance Calibration of High-Speed Serial Links
Tuesday, February 3 | 10:15 am – 10:55 am
Bilal Ahmad, Technical Leader, Cisco Systems Canada
Jayanthi Natarajan, Technical Leader, Cisco Systems
Eric Tran, Hardware Engineer, Cisco Systems
As part three of the principal author’s series on the subject, we present an empirical method of evaluating high-speed serial links. Test cards are built implementing several hundred variations of the channel types expected in the real system; these channels are excited by the SerDes transceivers under consideration or an earlier version of the same. Performance is measured in terms of an available metric that is measurable and sufficiently dependent on the noise margin. This metric is then empirically correlated with the actual performance using statistical averages, spreads, and trends, and its relationship with the physical attributes of the channels tested.