Schedule
7-TA2
Practical Analysis of Backplane Vias for 5 Gbps and Above
Tuesday, February 3 | 9:20 am – 10:00 am
Eric Bogatin, President, Bogatin Enterprises
Sanjeev Gupta, Signal Integrity Specialist, Agilent
Mike Resso, Signal Integrity Measurement Specialist, Component Test Division, Agilent
Bert Simonovich, Signal Integrity and Backplane Architecture, Nortel
Accurate, verified models for vias in a multilayer circuit board are necessary to predict link performance in the GHz regime. This paper describes the methodology of using a 3D full-wave field solver and measurements on a test vehicle to build high-bandwidth behavioral models of long vias. These models can be further reduced in complexity by approximating them with simple topology-based, scalable models that can be used for system simulation. These simple models also provide valuable insight into the root cause of performance limits and how to overcome them.