Gary Yip, Principal Engineer, Rambus
Ken Chang, Senior Manager, Rambus
David Nguyen, Vice President, Rambus
Chuck Yuan, Engineering Director, Rambus

Parallel and serial data links operating at or faster than 10 Gbps requires a low phase–noise reference clock source. An alternative to such a clock chip is to reduce the jitter of a low-cost clock part using band pass filtering already available in a common used clocking architecture for data links. This paper presents experiments that quantify the band pass filter in terms of the UI percentage of data openings. Results showing the reduction of random jitter will also be included.