Joshua Fender, Supervising MTS, Software, Altera
Navid Azizi, Senior Software Engineer, Altera

The push to higher interface bandwidths has increased the pin count and signaling rates of modern FPGAs. A side effect of these increases is higher simultaneous switching noise (SSN). This paper presents an SSN–aware methodology for defining and optimizing PCB design rules that ensure system reliability. Problems that used to be found during system qualification in the lab can now be identified and fixed before fabrication even begins. The result is lower cost and faster time to market.