Vishram Pandit, Senior Analog Engineer, Intel
Myoung Choi, Design Engineer, Intel
Hsiao-ching Chuang, Intel
Ashish Pardiwala, Design Engineer, Intel
Ruhul Quddus, Intel

In this paper, we describe the power integrity design and characterization for a single-ended I/O interface through noise, eye margin, and jitter measurements. The frequency domain techniques are used for designing the I/O PDN. For PDN characterization, on-chip PDN elements are extracted through the on-wafer VNA measurements. The peak-to-peak voltage noise is measured on chip at the driver. The eye margin reduction and jitter induced due to power noise are characterized versus frequency. The overall signature of the time domain noise, eye margin reduction, and jitter response is well correlated with simulated impedance response.