Hsing-Chou Hsu, Deputy Manager, VIA Technologies
Chi-Hsing Hsu, Manager, Azurewave Technologies
Jack Lin, Regional Manager, Sigrity

A broadband analysis methodology is described for the design of a PDS for high-speed IO, including chip, package, and board. Rather than a more traditional time domain simulation, the IO PDS is characterized through frequency domain impedances, accounting for the PDS coupling that drives simultaneous switching effects for adjacent IO cells. Chip-package-board co-simulation, what-if analysis, and decap optimization are performed to craft a low PDS impedance response throughout the system. This methodology has the advantages of greater insight for the system-level influence of each domain as well as enabling resonance effects to be avoided at critical system frequencies.