Joong-Ho Kim, Senior Signal Integrity Engineer, Rambus
Wendem Beyene, Senior Principal Engineer, Rambus
Dan Oh, Senior Engineering Manager, Rambus
Ralf Schmitt, Senior Engineering Manager, Signal Integrity, Rambus
Arun Vaidyanath, Engineering Manager, Rambus
Chuck Yuan, Engineering Director, Rambus

The feasibility to implement a memory interface with a data rate of 2.4 to 3.2 Gbps for an HDTV system into a low-cost LQFP package is analyzed. Due to the large inductance of the package lead frame, power integrity is a major challenge for this design. While single-ended systems such as DDR and GDDR are very difficult to operate at Gb data rate using this low-end LQFP package, differential signaling systems such as XDR memory interface suffers less from supply noise and are more suitable for highly inductive package designs. Through a package/chip co-design approach, carefully balancing the jitter generated by supply noise on different supply rails of the chip, this paper demonstrates that the XDR system can operate safely up to 3.2 Gbps.