Wheling Cheng, Technical Leader, Cisco Systems
Shen Lin, Chief Technology Officer, Apache Design Solutions
Aveek Sarkar, Vice President, Product Engineering/Support, Apache Design Solutions
Ji Zheng, Director of Engineering, Apache Design Solutions

This paper demonstrates an optimum methodology to capture the worst-case switching activity when performing the power integrity analysis for the core power of ASIC. The key approach is to capture the resonant frequency of the complete PDN, including the chip, package, and board. From the FFT of the switching activity, the worst-case pattern can be obtained by identifying the major frequency content that coincides with the resonance frequency of the PDN. The feasible process flow is demonstrated through an ASIC design. The results illustrate the interaction between the switching activity and the chip/package/board design.