Jeremy Popp, Mixed Signal ASIC Design Leader, Solid State Electronics Development, The Boeing Company
Roger Brees, Solid-State Electronics Development, The Boeing Company
Richard Shi, Chief Technology Officer, Orora Design Technologies
Warren Snapp, Director, Solid-State Electronics Development, The Boeing Company
Ying Wei, Senior Member of Technical Staff, Orora Design Technologies

This paper presents a complete performance verification methodology applied to a 10 Gbps XAUI SerDes design implemented in 90 nm CMOS. An industry-first EDA modeling platform automates generation and calibration of silicon-accurate SerDes behavioral models using transistor-level simulations over process, voltage, and temperature corners. The calibrated SerDes models enable validation of system-level performance, including deterministic and random jitter sensitivity, backplane compliance, eye diagram degradation, and estimated bit-error rate. This work provides designers with a new system-level, mixed-signal validation capability that provides 100x to 1000x simulation speed-up with user-adjustable accuracy. Silicon measurement validation against behavioral model simulation results is described.