Chip-to-chip communication is increasingly being handled by serial links. The data throughput is increasing at a fast pace and is approaching tens of Gbps. Communication at these speeds poses unique challenges for the transmitter, receiver, and physical channel carrying the communication. The channel components from the transmitter to receiver should be designed with a minimum of discontinuities. Crosstalk between channels and within channels is of particular concern.
Considerations of jitter have emerged as a major design factor in these high-speed channels. The raw communication error BER is related to jitter. In addition, testing and verification of channel compliance with standards has become a challenge.
In this panel we will discuss how channels can be designed with minimum of jitter and the state of signal modeling of the complete system from the transmitter to receiver. The system modeling includes algorithmic device modeling, which has recently standardized as IBIS Algorithmic Modeling Interface (AMI). We will also discuss the state of passive channel modeling at multi-gigahertz rates and testing and verification methods.
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Moises Cases
Distinguished Engineer, STG
IBM |
Mr. Cases has 38 years of progressive experience in VLSI chip and package designs, in system-level electrical and package designs, and in complex project and people management. At IBM, he is responsible for system electrical design and integration of modular and blade servers, signal and power distribution integrity, and system-level timings of complex multiple board system designs. He obtained an M.S.C.E. from Syracuse University in New York in 1979, an M.S.E.E. from New York University in 1973, and a B.S.E.E. from City College of New York in 1969. He is a senior member of IEEE. |
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Om P. Mandhana, PhD
Chair, IEEE-CPMT Chapter in Austin
Networking and Multimedia Group Freescale Semiconductor |
Dr. Mandhana is a Senior R&D Engineer in the Networking and Multimedia Group (NMG) of Freescale Semiconductor, Austin, Texas, since 1998. His current responsibilities include lead and develop methodology and tools strategy for chip, package, board, and interconnect co-design modeling and simulations capability to address power integrity and signal integrity issues related to NMG products. |
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Bilal Ahmad
Technical Leader
Cisco Systems Canada
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Dr. Ahmad works as signal integrity lead for Cisco Systems Canada. During his professional career he has worked as software engineer for the Jet Propulsion Laboratories, as research associate for Stanford University, as visiting faculty for the Center for Advanced Studies in Engineering – Islamabad, and as founder and entrepreneur in a privately funded effort to develop EDA tools for high speed serial interfaces. |
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Mohammad Ali
Principal Scientist, Signal Integrity and Advanced IC Packaging
Broadcom |
Dr. Ali is a Principal Scientist at Broadcom Corporation, where he works as a Signal Integrity Engineer responsible for various on-chip, off-chip and package SI issues. He has over 20 years of professional experience in various industries. |
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Kumar Keshavan
Tool Developer
Sigrity |
Dr. Keshavan joined Sigrity in February 2008 and has more than 24 years of experience in the EDA industry. He has worked at Telesis, then Valid, and finally Cadence from 1984–1998. At Cadence, Dr. Keshavan was the architect for specctraquest tool. He wrote the time domain simulator tlsim, which lies at the core of specctraquest. Earlier, Dr. Keshavan was responsible for analyzing heat transfer in printed circuit boards. He rejoined Cadence from 2003 to 2008 and developed the company’s Channel Analysis tool. |
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Dmitry Smolyansky
Tool Developer
Tektronix |
Mr. Smolyansky spent his professional career in the instrumentation and measurement industry, working with high-speed time domain reflectometry oscilloscopes and frequency domain network analyzers. He is currently responsible for TDR and S-parameter serial data measurement solutions at Tektronix. During his professional career, Mr. Smolyansky has accumulated significant experience in the area of high-frequency measurements and gigabit interconnect measurements and modeling. He has published a number of papers and taught short courses on interconnect measurements and modeling. |
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Lawrence Williams
Director, Business Development
Ansoft |
Dr. Williams is responsible for building strategic relationships with leading Ansoft customers and business partners. His responsibilities include the strategic direction of Ansoft’s products for microwave, wireless, and high-speed electronic component design. Dr. Williams is an expert in the application of electromagnetic field simulation to the design of antennas, microwave components, and high-speed electronics. He has more than 19 years of experience in the fields of electromagnetics and communications engineering and has published numerous technical papers on the subject. |



























