Advanced technologies such as SiP, through silicon via, and 3D-IC are enabling designers to put more functionality into a single IC package. With the IC packaging cost rising, the ability to stack multiple dies on a single substrate seems to be a very cost-effective solution. However, designers are facing challenges when designing and validating multi-die chips, as issues associated with power, SI, reliability, thermal, stress, etc., are further exacerbated. Existing solutions are unable to address these challenges, but can existing tools be enhanced to deliver new methodology and design flow, or is a revolutionary solution required? Implementation tools need to allow designing of multiple dies along with the package in a single environment. Analysis and signoff tools need to be able to handle the complexity associated with multi-die and package while analyzing the impact of various noise, including power, signal, temperature, and EM. And the software providers need to create a channel between IC and package design teams to enable collaboration. This panel will discuss the challenges and required solutions.

An-Yu Kuo Chief Architect Apache Design Solutions

Dr. Kuo's primary focus at Apache is IC/package/system co-design and co-simulation. He joined Apache Design Solutions after Apache acquired Optimal Corporation in 2007. Dr. Kuo is a co-founder of Optimal Corporation. There, he led developments of several analysis tools for electrical, thermal, and mechanical characterization of electronic packaging. Prior to founding Optimal Corporation, Dr. Kuo worked at a couple of consulting companies, providing package simulation services to electronics industries.

Richard Goering Editor-In-Chief SCDsource.com

Mr. Goering is editor-in-chief of SCDsource.com, an on-line publication for system and chip designers. He has been writing about EDA and chip design since 1985, and he served as EE Times' EDA editor from 1990 to 2007.

Brad Griffin Product Marketing Director, SiP, IC Packaging, and PCB High-Speed Solutions Cadence Design Systems

Brad Griffin is product marketing director, SiP, IC Packaging, & PCB High-Speed Solutions, of Cadence Design Systems PCB & IC Packaging User Segment. He has 17+ years of experience in EDA technologies that enable IC packaging & PCB system designs. Griffin is a graduate of Arizona State University.

Rajen Murugan Signal Integrity Engineer Texas Instruments

Dr. Murugan's focus is on developing electrical and physical co-design/simulation flows for wireless and RF designs. He holds patents in electrical impedance tomography and signal integrity. He is published in refereed journals.

Andy Tseng Director ASE

Mr. Tseng leads the dynamic substrate design and packaging application teams at ASE, and provides packaging design, thermal/electrical study, package assembly, qualification, and failure analysis support. He holds MS in Physics from Northern Illinois University and MSEE from Santa Clara University.

Vincent Wang Vice President, Package Technology Altera

Dr. Wang is in charge of new product package planning, packaging technology development/evaluation/implementation, manufacturing engineering, test implementation, and subcontractor management at Altera. His previous employments include Fujitsu, Applied Materials, DEC, and HP.