It is increasingly difficult to create a complex SoC device without using some intellectual property (IP) cores for major portions of the design. Creating on-chip processors, interfaces, or complex algorithmic subsystems from scratch are just too cost-prohibitive, create unnecessary risks, and detract from the creation of the most critical, differentiating capabilities of the new product.

Given that IP is going to be an important part of the design, how do designers find, evaluate, and select between different IP cores? Are there new tools and/or techniques that can help with this process? What are IP suppliers doing to make this easier for the designer? This panel session will ask and offer some answers to the types of questions. Representatives from IP companies, designers, and some Web-based selection portals will offer their thoughts and suggestions.

Raghavan Menon Director of Engineering, ASIP Virage Logic

Mr. Menon is responsible for all aspects of IP engineering development for memory controllers, PHY, DLL, and IOs for a wide range of industry standards, including DDR/DDR2/DDR3/MobileDDR and GraphicsDDR. He joined Virage Logic when it acquired Ingot Systems, where he was a co-founder. Mr. Menon has authored several technical papers and has presented at DesignCon and other conferences several times over the last four years.

Gary Delp Distinguished Engineer LSI Logic Corporation

Dr. Delp is a distinguished engineer working out of the CTO office at LSI. As one of three architects of the Low Power Coalition and vice-chair of the IEEE P1801 working group, he is in a unique position to provide insight into interoperability needs and potentials.

Kalar Rajendiran Senior Director, Marketing eSilicon Corporation

Mr. Rajendiran is the senior director of marketing for eSilicon Corporation, where he is responsible for the company’s product marketing, marketing operations, and semiconductor IP strategy. He is a key member of the team that launched eSilicon as a pioneering company with an innovative business model.

Gabriele Saucier President Design and Reuse

Dr. Saucier received her PhD from the University of Grenoble, where she was a professor and headed a research lab on Integrated System Design. She has published more than 350 papers in the design and EDA fields. Dr. Saucier is an IEEE fellow for her contributions in synthesis, test generation and fault tolerance. In the 1990s she founded a synthesis company, IST (Innovative Synthesis Technologies), mainly dedicated to FPGA synthesis, and in 1997 Design and Reuse, dedicated to IP-based design.

Adam Traidman Group Marketing Director, Chip Planning Solutions Organization Cadence Design Systems

Mr. Traidman recently joined Cadence through the acquisition of Chip Estimate Corporation, where he served as president and chief executive officer for the past four years. Prior to that, he ran North America sales for Hier Design. Mr. Traidman had previously held a variety of technical and management positions in deep sub micron IC implementation at Texas Instruments, Adaptec and the NASA Jet Propulsion Laboratory.

Featured Event

This session is part of the IP Summit at DesignCon, featuring dedicated educational sessions and technology demonstrations on semiconductor IP and system-on-chip design. Click here for a complete lineup of IP Summit programming.