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Schedule
Technical Panel
How Can Semiconductor Designers Meet High Performance/Low Power Requirements for Customers by Providing Greater Choice at Advanced Technology Nodes?
Monday, February 2 | 4:45 pm – 6:00 pm

To meet growing demands for high-performance and low-power chips, design technology and process technology must be co-optimized to deliver new innovations in chip design targeting advanced process-technology nodes. The panel will explore how to combine design technology, methodology, IP/library, process technology, and design services in several unique and differentiated approaches to deliver more value-added solutions and services to semiconductor designers. A number of innovative solutions and services resulting from close collaborations between companies in the design/foundry ecosystem will be illustrated. The panel will also explore several new collaboration models targeting sub-45 nm technologies.

The panel would include members from the following types of companies to demonstrate design-chain collaboration: a pure-play foundry, a third-party IP provider, an EDA company, and a major IDM or fabless customer.

Chairperson
tom quan
Tom Quan
Deputy Director, Design Service Marketing
TSMC
Mr. Quan has more than 20 years of experience in technical and marketing roles in the semiconductor and EDA industries. He was vice president of marketing at Applied Wave Research. Prior to AWR, he was a vice president at Cadence, where he oversaw strategic marketing and business development activities for initiatives targeting SoC designs and foundry libraries.
Speaker
Kenneth Brock
Kenneth Brock
Director of Physical IP Marketing
Virage Logic
Mr. Brock is responsible for driving Virage Logic’s logic products to meet the requirements for advanced node IP solutions that deliver optimal performance, power, area and yield. He has 25+ years experience in the IP and EDA industries serving in marketing, professional services, and product development roles.
Kurt Huang
Kurt Huang
Marketing Director
Global Unichip Corp.
Dr. Huang has been with Global Unichip Corp. since 2006 as the marketing director. He has extensive working experience with various IP vendors and service providers to optimize the efficiency of the silicon supply chain to provide increased value to end customers.
kevin kranen
Kevin Kranen
Director, Strategic Alliances
Synopsys, Inc.
Mr. Kranen’s current responsibilities include building leading-edge industry design flows and methodologies with a number of key Synopsys partners, providing end-users with the lowest cost and lowest risk design solutions for advanced SoCs. Over his 19 years of experience with Synopsys, Kevin has held a number of relationship management and product management roles.
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