Mike Li, Principle Architect/Distinguished Engineer, Altera

This TecForum reviews the latest design and verification developments, as well as architecture, circuit, and process technology advancements for high-speed links, with an emphasis on jitter and signal integrity for ~10 Gbps high-speed I/Os. Example studies on design and validation methods will be presented. Practical issues of design tradeoff, multiple I/O standards support, jitter reduction, signal integrity mitigation, and advanced verification methodologies will be covered.