Andrew Pizali, Consultant
Avi Ziv, IBM
Badri Gopalan, Principal Engineer, Synopsis

In a consumer electronics market that measures time from product conception to delivery in months and is driven by seasonal sales cycles, first-pass, fully functional silicon is the ultimate determinant of product success. Functional verification remains the least predictable process in the design flow, largely due to the lack of a rigorous definition of the verification problem. A comprehensive verification plan derived from the product specification is the foundation of a metric-driven process that quantifies the verification problem and defines its solution.

This tutorial addresses the verification of a modern SoC having substantial software content using such a quantitative approach. The student will learn how to analyze a specification to create a verification plan that describes the verification problem, quantifies it using measurable metrics, specifies the solution to the problem, and facilitates automation of functional closure. You will learn how to analyze a specification with an eye toward identifying product features and their associated attributes and behavioral requirements. Quantifying the verification problem through coverage model design is demystified. We describe how to choose the appropriate verification technique (e.g., simulation, formal, hybrid) for each feature and design its application. The use of verification plan automation, allowing the verification plan to be used to directly control and measure the verification process is addressed.

Advanced topics discussed in the tutorial include:

• Sophisticated modeling and planning for registers at multiple abstraction levels
• Metric measurement and analysis tools for application performance
• Automatic planning and execution of power-related metrics for power-managed designs