Daniel Wu, Business Development Engineer, Ansoft

The IEEE 802.3 Ethernet Higher Speed Study Group is charting the course to 40 Gbps and 100 Gbps serial rates. While initial efforts have focused on four 10 Gbps data channels, this paper examines the possibility of a single 40 Gbps serial channel. Migration to 40 Gbps via a single channel holds the promise of reduced complexity and cost. This paper outlines the challenges of designing such a channel based on the 65 nm bulk CMOS technology node and presents a full channel model that includes a pre-emphasized, serialized driver and a receiver with equalization and clock and data recovery.