Jim Choate, Product Manager, DTD – Scopes, Agilent Technologies

As serial bus interface speeds climb past 5 Gbps, secure margins for reliable system operation are substantially reduced. In design validation you work to verify margins for electrical signal integrity by measuring parameters such as jitter and its constituent components of random and deterministic, signal amplitudes, and common-mode voltage. This paper describes how to reduce the margin you give up to your test fixture through the application of fixture de-embedding techniques adapted to real-time oscilloscope measurements. These techniques are customized to meet the unique conditions associated with test fixtures for high-speed serial buses such as PCI Express Gen 2.