Philippe Sochoux, EMC Design Manager, Central Engineering, Cisco Systems
Alpesh Bhobe, EMC Design Engineer, Cisco Systems
Jinghan Yu, EMC Design Engineer, Cisco Systems
Morris Hsu, Intern, Cisco Systems Morris Hsu, Intern, Cisco Systems

SerDes differential pairs operating in the multi-GHz range are replacing slower source synchronous interfaces in many high-end digital networking applications. Detailed EMI layout rules for routing SerDes differential pairs are quasi-nonexistent. At 6+ Gbps operating speed, small layout imperfections (e.g., bends, loopbacks to adjust skew) do cause impedance mismatch and may contribute to EMI. As a result, there is a strong need to study, expand, and improve the EMI layout rules that governed slower, sub-GHz interfaces. In this paper, we will numerically investigate and catalog these small layout imperfections on SerDes pairs that may cause unwanted EMI in the multi-GHz range.