DesignCon 2009
imagery
DesignCon 2009 Tracks
  • Chip-Level Architectural and Functional Design
  • Functional and Performance Verification
  • Chip-Level Physical Design and DFM
  • Chip-Level Electrical and Package Design
  • PCB and Passive Component Technology
  • High-Speed Parallel Interface Design
  • Multi-Gigabit Serial Interconnects
  • High-Speed Timing, Jitter, and Noise
  • High-Speed Signal Processing, Equalization, and Coding
  • Power Integrity and Power-Aware Design
  • Electromagnetic Compatibility and Interference
  • Test Fixturing and Measurement Methodology
  • RF and Signal Integrity
  • Chip/Package/Board/System Co-Design
  • Business and Engineering Impacts
Chair: James Lin
Who Attends DesignCon
Job Titles Key Job Functions
Industry Segments
IEC
2008 highlights
Exhibit Space Available
Rebook PDF