Regression automation Solution — Aldec has removed the traditional product verification barriers imposed by HDL simulator license availability by offering highly cost-effective bundles of batch-mode, mixed language simulators for simulation server farms. Companies can now verify their designs fast and efficiently, using mixed-language simulator licenses that run on server farms with 32 and 64 bit CPU's, without crating and maintaining a complex scripted environment. Set-up and control is automated through a web-enable control console.

Pure SystemC designs and mixed HDL-SystemC designs can be debugged using one, unified environment - Aldec's Riviera-PRO. You can set breakpoints both in HDL code and in C++ code, or step through HDL and SystemC statements in the same editor. Various debugging tools will show both HDL and SystemC hierarchy and values of HDL and SystemC objects. The call stack can be examined both for HDL subprograms and C/C++ function calls.

Complete FPGA design and verification environment that include, graphical design entry, project management, documentation and HDL verification. It provides engineers and design teams with tools for efficient FPGA vendor-independent design creation, implementation and verification from one common design environment. Co-simulation interface to Matlab and Simulink facilitates designs with DSP.