High-speed I/O link speed continues to increase, with most of the link I/O speeds being at about 5 Gbps at present and moving to about 10 Gbps for the their next generations. Jitter and signal integrity has become one of the most difficult challenges for designing and verifying I/O link components and systems at those multiple rates. This tutorial will review some of the latest design and verification developments, as well as technology advancements, with an emphasis on jitter and signal integrity of computer high-speed I/Os (e.g., PCI Express, serial ATA), as well as network high-speed I/Os (e.g., GBE, OIF). Examples and case studies on link system design and validation methods will be presented under the condition that its subsystems of transmitter, channel, receiver, and reference clock are predefined. Practical issues of design tradeoff, technology selection, multiple I/O standards support, and cost optimization will be covered.