TF-MP1
Design of High-Performance Adaptive FIR Filters Using FPGA
Monday, February 4 | 1:30 pm – 4:30 pm
Chang Choo, Professor, San Jose State University
Adaptive FIR filters are an essential part of many DSP systems, including echo cancellers, channel equalizers, and noise cancellers. In this tutorial, we present how to design high-performance adaptive FIR filters on FPGA using HDL and Matlab tools. Various parallel filter design examples are presented that use tens to hundreds of multipliers available on FPGAs. In addition, the embedded adaptive filtering system and SoC, consisting of flexible LMS cores and an FPGA soft processor such as Xilinx MicroBlaze, is presented. We will also analyze the bit-level scalability at various locations within the internal data path, with respect to system performance.