TF-MA5
Tools for Reducing the Hidden Costs in the IP Supply Ecosystem
Monday, February 4 | 9:00 am – Noon
Dr. Raminderpal Singh, Senior Technical Staff Member, IBM; IPecosystem Technical Lead, GSA
Walter Ng, Sr. Director, WW EDA and IP, Chartered Semiconductor Manufacturing, Inc.
David Schwan, Engineering Manager, CAD and Layout, RF Micro Devices (RFMD)
Adam Traidman, President and CEO, Chip Estimate Corporation
Walter Ng, Sr. Director, WW EDA and IP, Chartered Semiconductor Manufacturing, Inc.
David Schwan, Engineering Manager, CAD and Layout, RF Micro Devices (RFMD)
Adam Traidman, President and CEO, Chip Estimate Corporation
GSA is pleased to host this interactive tutorial session focused on the IP ecosystem, having heard in many forms and from companies throughout the supply chain that relationships between IP vendors, IP integrators, EDAs, and foundries are sometimes complex, difficult, and even frustrating. Based on this industry need, GSA has invested in a multi-year project called the IPecosystem Tool Suite (IPe) to create a simple tool to address many levels of issues and challenges.
The tutorial session will include the following:
- What problems are faced today in IP evaluation?
- Where are the hidden costs to buying new IP or designing in new technologies?
- What is needed?
- IPe Tool Suite overview, demo of Hard IP Quality & Licensing Risk Assessment tools, applicability to chip integrators/IP vendors/foundries
- Overview of key Industry IP trends
- Next steps: Tools for reducing hidden costs in manufacturability and technology