Many of the problems in the semiconductor IP industry, perceived and real, can be traced to a lack of standardization in how IP is developed and transferred to users and how IP and IP vendors are qualified by those users. IP integration is still far from turnkey for most companies and is one of the reasons integrators are reticent about accepting IP from either large or small providers. VSIA did a nice job with their quality IP metric (QIP), but acceptance of the metric has been slower than desired and their work is now being transferred to the IEEE.

With an eye toward both IP technology and business issues, who should be developing the industry's standards for IP development, transfer and integration, and what needs to be done to ensure widespread acceptance of these standards by the developer and integrator communities as well as other industry factions?

Jim Lipman Vice President, Client Services Cain Communications

Cain Communications is an agency providing marketing communications services to semiconductor, IP, EDA, and other high-tech companies of all sizes. Dr. Lipman's prior work experience includes editorial positions at EDN and TechOnLine, the latter where he was content director; marketing and training positions at VLSI Technology; and various engineering jobs at Hewlett-Packard and Texas Instruments. Mr. Lipman has an electrical engineering doctorate from SMU and an M.B.A. from Golden Gate University.

Victor Berman President and CEO Improv Systems

Prior to coming to Improv, Mr. Berman was group director for Language Standards at Cadence Design Systems, Inc., where he was responsible for the corporate language strategy and played a role as an industry driver promoting standards-based design flows from the tool supplier point of view. Before Cadence, he headed sales and marketing at Improv Systems, Inc. Mr. Berman's formal training was in language design and electrical engineering in the interdisciplinary computer science graduate program at Carnegie Mellon University.

Gary Delp Distinguished Engineer LSI

Dr. Delp spends his time working on design and IP reuse, inside of a design, across designs, and across the economic ecosystem. He is the technical director of The SPIRIT Consortium, and the CTO of the VSI Alliance. Dr. Delp is also the vice chair of the IEEE study group on common power formats. Previously he worked at Redback Networks as a principal engineer and spent 12 years at IBM supporting the microelectronics and server businesses as well as the AS/400 product. Dr. Delp's work on standards involves organizations such as IETF, the ATM Forum, IEEE 802, Network Processor Forum, and Optical Interconnect Forum.

Bill Martin General Manager Mentor Graphics, IP division

Mr. Martin has more than 25 years of experience in consulting, product design, and project management and holds five patents. He joined Mentor in 2000 as the U.S. director of Mentor Consulting and promoted to vice president of Mentor Consulting. Mr. Martin had previously worked for Synopsys, VLSI Technology, and Mostek. Martin holds an M.B.A. in marketing/finance from the University of Texas at Dallas and a B.S. in computer engineering from the University of Illinois at Urbana-Champaign.

Kathy Werner IP Strategy and Business Manager Freescale Semiconductor

Ms. Werner has led IP Strategy & Business at Freescale and been involved in design, NPI, and management at several other companies, including wireless, processor development, consumer and computing, and military, in both direct and consulting roles. She also has experience in standards development, including time as president of the VSIA industry consortium and vice chair of the IEEE DASC committee. She also chaired the VSI Alliance Quality IP Pillar and led the development and introduction of the quality IP (QIP) metric. She had published in Electronic Business, EETimes, Chip Design, and others and was the co-executive editor and contributor of an upcoming book on intellectual property.

Mobashar Yazdani Senior Engineer/Scientist ASICs Hewlett-Packard

Mr. Yazdani's position is in Global Sourcing and Procurement, as a program lead, for imaging SOCs for ASIC development and manufacturing. He joined HP in 1988 as a CPU designer on its first generation of CMOS RISC processors. Mr. Yazdani became a member scientist in HP Labs' VLSI group for the development of HP's Wide Word Architecture in and joined HP procurement's R&D group for assessment of emerging technology, IP, and foundries. He managed the ASIC/ASSP technology center in HP's supply chain operations for ASIC supplier assessments and leveraging ASIC development. Mr. Yazdani holds B.S.E.E. and M.S.E.E. degrees from University of Texas at Austin and University of Kentucky.