A panel of industry experts discusses how the industry and customers are addressing today's and tomorrow's verification challenges. Moderated by Gary Smith, the industry's pre-eminent EDA analyst, the event will feature panelists from Synplicity, Synopsys, and prototyping users. Despite new verification methodologies such as assertion-based verification, random-constraint verification, and dynamic formal verification, designer productivity continues to depend on the raw performance of verification tools.

At the implementation level, the highest performance is provided by FPGA-based prototypes. Until now, such prototypes lacked a productive and elegant software environment to allow users to take advantage of this speed. Thus, there's a productivity gap. Industry panelists will debate and offer insight on how, and if, FPGA-based prototyping will need to evolve to solve the rising verification crisis. More important, will FPGA-based prototyping emerge as the standard for high-performance verification?

Gary Smith Founder and Chief Analyst Gary Smith EDA

Prior to his current position, Mr. Smith was the managing vice president and chief analyst of the electronic design automation service, design and engineering cluster at Gartner Dataquest. While at LSI Logic, he became an evangelist for the RT-level design methodology. Mr. Smith is currently a member of the Design TWG for the International Semiconductor Road Map (ITRS), editorial chair of the IEEE Design Automation Technical Committee (DATC) and serves on the DAC Strategic Committee. He earned his bachelor of science degree in engineering from the United States Naval Academy.

Tom Borgstrom Director, Solutions Marketing Synopsys

Mr. Borgstrom joined Synopsys in 2003 and is responsible for system-to-silicon verification solutions marketing. Prior to Synopsys, he was vice president of marketing at TransEDA and has held senior sales, marketing, and applications roles at Exemplar Logic, Duet Technologies, and CrossCheck Technology. Mr. Borgstrom started his career as an ASIC design engineer with Matsushita in Osaka, Japan, and has a B.S.E.E. and M.S.E.E. from The Ohio State University.

David Garau Senior Staff Engineer Teradici Corporation

Mr. Garau currently leads a team of hardware engineers that is working on emulating and validating Teradici's next-generation SOC device. He previously held key positions at Advanced Micro Devices (AMD) and Motorola Semiconductor, leading several microprocessor development teams. He also worked on the validation of multimillion-gate ASIC devices at PMC-Sierra. Mr. Hulett also previously served as the vice president of research and development for Austin-based Si Solutions, Inc. He received his B.S.E.E. from Oklahoma State University. He received his B.Eng. in electrical engineering from the University of Victoria.

Terry Hulett Vice President of Architecture and Hardware Engineering Neteffect

Mr. Hulett leads NetEffect's innovation efforts, leveraging more than 25 years of semiconductor design experience. He previously held key positions at Advanced Micro Devices (AMD) and Motorola Semiconductor, leading several microprocessor development teams. Mr. Hulett also previously served as vice president of research and development for Austin-based Si Solutions, Inc. He received his B.S.E.E. from Oklahoma State University.

Juergen Jaeger Senior Director of ASIC Verification Marketing Synplicity

Mr. Jaeger joined Synplicity in 2007 after spending more than 10 years in various marketing positions at IKOS Systems and later Mentor Graphics. He started his career as a hardware designer and has more than 20 years of experience in marketing and product marketing of design and verification solutions for ASICs and FPGAs. He studied electrical engineering at the Fachhochschule of Kaiserlautern in Germany and computer science at the University of Hagen in Germany.