Technical Panel
Is Coverage the Best Metric for Verification Closure?
Monday, February 4 | 4:45 pm – 6:00 pm
Coverage-driven verification is becoming increasingly popular. Coverage includes code coverage, functional coverage, and assertion coverage. The issues with coverage are as follows:
- Identifying metrics, especially for functional coverage and assertion coverage
- Deriving those metrics from the coverage data
- Analyzing those metrics for verification closure
Chairperson
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Faisal Haque
Director of Engineering
QUALCOMM
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Mr. Haque has more than 20 years of experience in high-level verification and design of complex networking hardware. He previously spent eight years at Cisco Systems and was involved in the architecture, design, and verification of ASICs for the CRS-1 core router. Mr. Haque is the former chair of the Systemverilog Assertions committee and is currently chairing the Unified Coverage Interoperability standards committee. He is the co-author of "The Art of Verification with VERA" and "The Art of Verification with SystemVerilog Assertions."
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Speakers
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Thomas Anderson
Product Marketing Director
Cadence
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Mr. Anderson's responsibilities include formal analysis, assertion-based verification, and SystemVerilog. His previous positions include director of technical marketing in the verification group at Synopsys, vice president of applications engineering at 0-In Design Automation, and vice president of engineering at Virtual Chips. Mr. Anderson holds an M.S. in electrical engineering and computer science from MIT and a B.S. in computer systems engineering from the University of Massachusetts at Amherst.
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Adnan Hamid
Founder and CEO
Breker Verification Systems
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Mr. Hamid has more than 15 years of experience automating functional verification using coverage model-driven functional scenario generation. Prior positions of his include managing AMD's system logic division, leading AMD's microprocessor verification group, and serving as subject matter expert in system level verification at Cadence.
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Shankar Hemmady
Principal Engineer
Synopsis
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Mr. Hemmady is responsible for verification planning, methodology, and management solutions. He has verified and tested, or managed the functional closure of 25 commercial chips during his tenure in the industry as an engineer, manager, and consultant at AMD, Cirrus Logic, Fujitsu, Hewlett-Packard, Intel, S3, Sun, and Xerox. Mr. Hemmady co-authored a best-selling book published by Springer, "Metric Driven Design Verification: An Engineer's and Executive's Guide to First Pass Success." He is currently working on a second book focused on predictable verification convergence.
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Narayanan Krishnamurthy
Director of Methodology
Nusym Technology
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Prior to Nusym, Mr. Krishnamurthy was senior staff manager of the verification methodology team at QUALCOMM and principal staff scientist at Freescale. He has more than 16 years of experience in the areas of hardware-software design, verification, and EDA methodologies for microprocessors and SOC designs. Mr. Krishnamurthy holds an M.S. and Ph.D. from the University of Texas at Austin and a BTech from the Indian Institute of Technology in India.
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Pete LaFauci
AE Consultant
Mentor Graphics
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Prior to Mentor Graphics, Mr. LaFauci was senior principal design engineer at Applied Micro Circuits Corporation in Cary, North Carolina, where he was responsible for establishing and setting company direction in functional verification and was instrumental in planning and rolling out a migration from proprietary verification tools to the IEEE SystemVerilog standard. Mr. LaFauci has held advisory and senior-level positions at IBM and several start-up companies. He received a B.S. in computer science and a minor in electrical engineering from Rensselaer Polytechnic Institute.
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Mercedes Tan
Staff Verification Engineer
Sun Microsystems
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Ms. Tan has been responsible for processor verification since 1996. Currently, she is working in the global formal verification group, where she is driving deployment of advanced formal verification tools and methodologies. Prior to that, Ms. Tan verified UltraSparc processors as a full-chip, functional verification engineer. She was a contributing participant in the Coverage Interoperability Forum, and now she is currently a member of the Accellera Unified Coverage Interoperability Standard (UCIS) group.
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