DesignCon 2008: Conference: Schedule Track

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By Date | By Track

Keynotes

Monday, February 4
12:30 pm – 1:00 pm	Monday Keynote Address
	Speaker: Joachim Kunkel Vice President and General Manager Synopsys

Tuesday, February 5
12:00 pm – 12:30 pm	Tuesday Keynote Address
	Speaker: Misha Burich Senior Vice President, Research and Development Altera

Wednesday, February 6
12:00 pm – 12:30 pm	Keynote Address
	Rick Cassidy President TSMC North America

Business Forums

Tuesday, February 5
8:30 am – 10:00 am	Business Forum Panel Managing Unit Costs: Methodologies and Processes to Lower Overall Chip Costs
	Chairperson: Adam Traidman President Chip Estimate Corporation
10:15 am – 11:45 am	Business Forum Panel Executive Views on the Turbulent FPGA Landscape
	Chairperson: Kevin Morris Journal Editor FPGA
2:00 pm – 3:30 pm	Business Forum Panel Ecosystem Environment for Starting a Semiconductor Company
	Chairperson: Steve Szirom Founder InsideChips
3:45 pm – 5:00 pm	Business Forum Panel Emerging Markets — Tackling Market Opportunities in India
	Chairperson: Elizabeth Corcoran Senior Editor, Technology Coverage Forbes.com

Wednesday, February 6
8:45 am – 10:20 am	Business Forum Panel Refining or re-defining the Analog Design Sign-Off Flow
	Chairperson: Gary Smith Founder and Chief Analyst Gary Smith EDA
10:30 am – 11:45 am	Plenary Panel Navigating the ASIC Manufacturing Landscape
	Chairperson: Kazu Yamada Vice President and General Manager, Custom SOC Solutions Business Unit NEC Electronics America
2:00 pm – 3:30 pm	Business Forum Panel Where Is the ROI for DFM?
	Chairperson: Mike Santarini Senior Editor EDN
3:45 pm – 5:00 pm	Business Forum Panel Designing a More Fulfilling Career
	Chairperson: John Epperheimer Partner St. Charles Consulting Group

Technical Panels

Monday, February 4
4:45 pm – 6:00 pm	Technical Panel Is Coverage the Best Metric for Verification Closure?
	Chairperson: Faisal Haque Director of Engineering QUALCOMM
	Technical Panel Challenges in Verification and Compliance of Serial Data Technologies
	Chairperson: Chris Loberg Senior Manager of Marketing Tektronix
	Technical Panel Understanding the Impact of 100G Ethernet
	Chairperson: Loring Wirbel Director and Senior Analyst, Market Intelligence Unit *EE Times*

Tuesday, February 5
3:45 pm – 5:00 pm	Technical Panel ASIC Verification
	Chairperson: Gary Smith Founder and Chief Analyst Gary Smith EDA
	Technical Panel High-Speed PCB Traces: What Is Their Real Performance?
	Chairperson: Istvan Novak Distinguished Engineer Sun Microsystems
	Technical Panel The Call for Industry Research on Next-Generation Electrical Signaling
	Chairperson: Lee H. Goldberg Senior Technology Editor EN-Genius.com

Wednesday, February 6
3:45 pm – 5:00 pm	Technical Panel IP Standards — Where Do We Go From Here?
	Chairperson: Jim Lipman Vice President, Client Services Cain Communications
	Technical Panel Advanced High-Speed Serial Channel Metrics
	Chairperson: Dave Brunker Technical Fellow Molex Incorporated
	Technical Panel Package Extraction, Modeling, and Simulation in IC-Packaging-Board Design
	Chairperson: Vikram Jandhyala Founder and CEO Physware, Inc.

Tutorials

Monday, February 4
9:00 am – Noon	TF-MA1 The Great EDA Cover-Up: Coverage Metrics Explained
	TF-MA2 Advances in Gigabit Channel Measurement-Based Characterization and Simulation
	TF-MA3 Chip, PCB, and Connector Technologies for Meeting Today's and Tomorrow's 10+Gb Signaling Requirements — a Report on Current Trends and Future Road Maps
	TF-MA4 Computational Electromagnetics: From Maxwell's Equations to Signal Integrity and System Design
	TF-MA5 Tools for Reducing the Hidden Costs in the IP Supply Ecosystem
1:30 pm – 4:30 pm	TF-MP1 Design of High-Performance Adaptive FIR Filters Using FPGA
	TF-MP2 Developing Interoperable Algorithmic Models Quickly — A Tutorial
	TF-MP3 Design and Verification for Jitter and High-Speed I/Os at Multiple Gbps
	TF-MP4 AdvancedTCA (ATCA) Platform Design and Applications: A New Day in Scalable Telecom System Deployment
	TF-MP5 The ABCs of System-Level Design

Technology Exhibition

Tuesday, February 5
12:00 pm	DesignVision Awards Ceremony

12:30 pm

Ribbon Cutting Ceremony

12:30 pm – 6:30 pm

Technology Exhibition

Networking Reception
5:00 pm – 6:30 pm

12:30 pm – 2:00 pm

Lunch Served on Exhibition Floor

Wednesday, February 6
12:30 pm – 6:30 pm	Technology Exhibition Networking Reception 5:00 pm – 6:30 pm

12:30 pm – 2:00 pm

Lunch Served on Exhibition Floor

Track 1 | Chip-Level Architectural & Functional Design

Tuesday, February 5
8:30 am – 9:10 am	1-TA1 How to Quickly Create Complicated Message Sequence Charts Automatically without Spending Money on Software
9:20 am – 10:00 am	1-TA2 Designing and Verifying Ratio Synchronous Clocks (RSC) for High-Performance Low-Power Processors
10:15 am – 10:55 am	1-TA3 ESL Driven Instrumentation Interfaces
11:05 am – 11:45 am	1-TA4 A Reset Control Apparatus for PLL Power-Up Sequence and Auto-Synchronization
2:00 pm – 2:40 pm	1-TP1 Design and Application of Embedded Waveform Viewing Technology for Integrated Circuits
2:50 pm – 3:30 pm	1-TP2 Methods for Configurable Hardware Design

Wednesday, February 6
8:45 am – 9:25 am	1-WA1 Multimedia Application Specific Engine Design Using High-Level Synthesis
9:40 am – 10:20 am	1-WA2 Evaluating Embedded Non-Volatile Memory for 65 nm and Beyond

Thursday, February 7
9:00 am – 9:40 am	1-THA1 On-Chip Instrumentation for In-System IP Validation of a 6 Gbps Serial ATA Platform Device
9:50 am – 10:30 am	1-THA2 HW/SW Partitioning Tradeoffs in 3G & WiMAX Wireless Base Stations
10:40 am – 11:20 am	1-THA3 Transaction Level Assertions in an Interface Definition Language

Track 2 | Functional and Performance Verification

Tuesday, February 5
10:15 am – 10:55 am	2-TA3 Hope Is Not a (Verification) Strategy — Coverage Model-Driven Functional Scenario Generation
11:05 am – 11:45 am	2-TA4 Bridging Block-Level to Top-Level CDC Verification: Hierarchical CDC Verification
2:00 pm – 2:40 pm	2-TP1 A Python-Based SoC Validation and Test Environment
2:50 pm – 3:30 pm	2-TP2 Sources of Non-Determinism in Microprocessors

Wednesday, February 6
2:00 pm – 2:40 pm	2-WP1 How to Find if My Checker Is Complete and Exhaustive — A Set of Guidelines Using Systemverilog and Memory Controller Example
2:50 pm – 3:30 pm	2-WP2 Mixed-Signal Integration: Functional Verification in the Presence of Linear Analog Components

Thursday, February 7
9:50 am – 10:30 am	2-THA2 Formal Verification Flow in FPGA Designs

Track 3 | Chip-Level Physical Design and DFM

Wednesday, February 6
8:45 am – 9:25 am	3-WA1 Using Programmable Logic for Receiver Offset and Yield Enhancement
9:40 am – 10:20 am	3-WA2 Packaging DfM into Design Service

Track 4 | Chip-Level Electrical and Package Design

Tuesday, February 5
2:50 pm – 3:30 pm	4-TP2 Simulations and Characterizations for GHz On-Chip Power Delivery Network (PDN)

Wednesday, February 6
2:00 pm – 2:40 pm	4-WP1 Process and Temperature Variations on Electrical Parameters of Wire-Bond BGA Packages: an Impact Analysis Using Simulation-Based DOE Methodology
2:50 pm – 3:30 pm	4-WP2 FPGA I/O Timing Variations Due to Simultaneous Switching Outputs

Track 5 | PCB and Passive Component Technology

Tuesday, February 5
8:30 am – 9:10 am	5-TA1 Utilization of Buried Capacitance(TM) — A Case Study
9:20 am – 10:00 am	5-TA2 Application of Foldy-Lax Multiple Scattering Method to Via Analysis in Multilayered Printed Circuit Board
10:15 am – 10:55 am	5-TA3 Modeling Issues and Possible Solutions in the Design of High Speed Systems with Signals at 20 Gbps
11:05 am – 11:45 am	5-TA4 Solutions for Causal Modeling and a Technique for Measuring Causal, Broadband Dielectric Properties
2:00 pm – 2:40 pm	5-TP1 ATE Interconnect Performance to 43 Gbps Using Advanced PCB Materials

Track 6 | High-Speed Parallel Interface Design

Wednesday, February 6
8:45 am – 9:25 am	6-WA1 A Fast Algorithm to Instantly Predict FPGA SSN for Various I/O Pin Assignments
9:40 am – 10:20 am	6-WA2 Challenges in Implementing DDR3 Memory Interface on PCB Systems — A Methodology for Interfacing DDR3 SDRAM DIMM to an FPGA
2:00 pm – 2:40 pm	6-WP1 Counting the Picoseconds: Integrating Timing, Signal, and Power Integrity Analysis
2:50 pm – 3:30 pm	6-WP2 Study of Signal and Power Integrity Challenges in High-Speed Memory I/O Designs Using Single-Ended Signaling Schemes

Track 7 | Multi-Gigabit Serial Interconnects

Tuesday, February 5
8:30 am – 9:10 am	7-TA1 The Impact of Common Mode Currents and Interconnect Inductance on the Signal Quality of Differential Signals in Multi-Board PCB Systems
9:20 am – 10:00 am	7-TA2 Data Mining 12-Port S-Parameters
10:15 am – 10:55 am	7-TA3 Demonstration of SerDes Modeling Using the Algorithmic Model Interface (AMI) Standard
11:05 am – 11:45 am	7-TA4 BladeServer 10 Gbps Ethernet Backplace Design with Equalization Using Statistical Channel Analysis
2:00 pm – 2:40 pm	7-TP1 Strategies for Coping with Nonlinear and Time Variant Behavior for High-Speed Serial Buffer Modeling
2:50 pm – 3:30 pm	7-TP2 Multi-GB/s Serial Channel Design Using a Hybrid Measurement and Simulation Platform

Wednesday, February 6
8:45 am – 9:25 am	7-WA1 The Need for Impulse Response Models and an Accurate Method for Impulse Generation from Band-Limited S-Parameters
9:40 am – 10:20 am	7-WA2 Aggregation of Crosstalk in Backplanes

Thursday, February 7
9:00 am – 9:40 am	7-THA1 In Situ Characterization of High-Speed Signaling Systems with On-Chip Measurements
9:50 am – 10:30 am	7-THA2 Performance Limitations of Backplane Links at 6 Gbps and Above
10:40 am – 11:20 am	7-THA3 A Design of Experiments for Gigabit Serial Backplane Channels

Track 8 | High-Speed Timing, Jitter, and Noise

Tuesday, February 5
8:30 am – 9:10 am	8-TA1 Analysis of Crosstalk Effects on Jitter in Transceivers
9:20 am – 10:00 am	8-TA2 Modeling a Phase Interpolator as a Delta-Sigma A/D converter
10:15 am – 10:55 am	8-TA3 Characterization of Gaussian Noise Sources
11:05 am – 11:45 am	8-TA4 Crosstalk Measurement, Extraction, and Validation in 10 Gbps Serial Systems
2:00 pm – 2:40 pm	8-TP1 A Novel Approach for Characterizing Pulse Width Shrinkage in High-Speed Digital Communications Systems
2:50 pm – 3:30 pm	8-TP2 Exploration of Deterministic Jitter Distributions

Wednesday, February 6
2:00 pm – 2:40 pm	8-WP1 PCI Express Timing Margins
2:50 pm – 3:30 pm	8-WP2 A Systematic Approach to Solving Clock Synthesis and Clock Recovery Problems in High-Data-Rate Serial Bus Systems

Track 9 | High-Speed Signal Processing, Equalization, and Coding

Tuesday, February 5
9:20 am – 10:00 am	9-TA2 Design Considerations in High-Speed SerDes (25Gbps)

Wednesday, February 6
8:45 am – 9:25 am	9-WA1 Semi-Analytic Performance of NRZ/PAM4/PR2 Modulation across 8.5-25 Gbps Backplanes with Analog Equalization
9:40 am – 10:20 am	9-WA2 Pre-Cursor ISI Cancellation
2:00 pm – 2:40 pm	9-WP1 Half-Rate Decision-Feedback Equalization — Di-Bit Response Analysis & Evaluation
2:50 pm – 3:30 pm	9-WP2 Multilevel Signaling in High-Density, High-Speed Electrical Links

Track 10 | Power Integrity and Power-Aware Design

Tuesday, February 5
8:30 am – 9:10 am	10-TA1 Impact of PCB Laminate Dimensions on Suppressing Modal Resonances
9:20 am – 10:00 am	10-TA2 High Bandwidth Modeling and Simulation of SSO Effects on Single-Ended Switching Performance of Complex FPGA System Designs
10:15 am – 10:55 am	10-TA3 Analyzing the Impact of Simultaneous Switching Noise on System Margin in Gigabit Single-Ended Memory Systems
11:05 am – 11:45 am	10-TA4 Pushing the Envelope without Tears: An Advanced Power Delivery Solution
2:00 pm – 2:40 pm	10-TP1 Using Full Wave Solvers for Practical Analysis of Capacitor Mounting Structures

Track 11 | Electromagnetic Compatibility and Interference

Tuesday, February 5
2:50 pm – 3:30 pm	11-TP2 Mode Conversion and EMI Performance of Shielded Cable Assemblies for 10 Gbps Data Transmission

Wednesday, February 6
8:45 am – 9:25 am	11-WA1 Heat Sink Design Flow for EMC
9:40 am – 10:20 am	11-WA2 Loaded Parallel Stub Common Mode Filter
2:00 pm – 2:40 pm	11-WP1 Cable EMI Characterization Using a Reverberation Chamber
2:50 pm – 3:30 pm	11-WP2 EMI Shielding of Cable Assemblies

Track 12 | Test Fixturing and Measurement Methodology

Tuesday, February 5
8:45 am – 9:25 am	12-TA1 Challenges and Solutions for Removing Fixture Effects in Multiport Measurements
	12-TA2 Broadband Resonant-Plate Permittivity Measurement Technique for Printed Wiring Boards Aided by Electromagnetic Simulations

Wednesday, February 6
8:45 am – 9:25 am	12-WA1 A Jitter Estimation Method for Cascaded, Programmable Phase-Locked Loops
9:40 am – 10:20 am	12-WA2 50 GHz End Launch Connector Test Boards: the Description of the Development of Coax to Grounded Coplanar Launches and Through Lines on 30 mil Rogers 4350 Material with Comparison to Microstrip
2:00 pm – 2:40 pm	12-WP1 High-Speed Serial Interconnect Imbalance
2:50 pm – 3:30 pm	12-WP2 Characterization Methodology for High-Density Microwave Fixtures

Thursday, February 7
9:00 am – 9:40 am	12-THA1 High-Speed Probe Interconnect Techniques
9:50 am – 10:30 am	12-THA2 Performance at the DUT: Techniques for Evaluating the Performance of an ATE System at the Device under Test Socket
10:40 am – 11:20 am	12-THA3 Frequency Domain Calibration: A Practical Approach for the Serial Data Designer

Track 13 | RF and Signal Integrity

Tuesday, February 5
10:15 am – 10:55 am	13-TA3 Study of Fundamental Limit and Packaging Technology Solutions for 40 Gbps Transceiver Package Design
11:05 am – 11:45 am	13-TA4 Issues of Frequency Content of S-Parameter Data for High-Speed Channel Evaluation
2:00 pm – 2:40 pm	13-TP1 Validation Methods for S-Parameter Measurement-Based Models of Differential Transmission Lines
2:50 pm – 3:30 pm	13-TP2 A New Test Fixture Crosstalk De-Embedding Technique Using Time-Domain Gating

Track 14 | Chip/Package/Board/System Co-Design

Tuesday, February 5
2:50 pm – 3:30 pm	14-TP2 Modeling FPGA Current Waveform and Spectrum and PDN Noise Estimation

Wednesday, February 6
8:45 am – 9:25 am	14-WA1 The Future of Multi-Clock Systems
9:40 am – 10:20 am	14-WA2 Interface Based Design Concepts for IC, PKG, PCB Co-Design
2:00 pm – 2:40 pm	14-WP1 Efficient Modeling and Design Optimization Methodology for Integrated Power and Signal Distribution in Digital Systems
2:50 pm – 3:30 pm	14-WP2 Techniques for Co-Design of the Power Supply Chain from IC to Printed Circuit Board

Track 15 | Business and Engineering Impacts

Tuesday, February 5
8:30 am – 9:10 am	15-TA1 Is Congress Killing Innovation?
9:20 am – 10:00 am	15-TA2 Case Study Using the VSIA QIP to Evaluate Internally Developed Information Property
10:15 am – 10:55 am	15-TA3 Lifecycle Cost Is a DIME — How to Make Build/Buy Decisions
11:05 am – 11:45 am	15-TA4 ASIC 2-0
2:00 pm – 2:40 pm	15-TP1 BDU — A Complexity Measure for a Board Design Project