DesignCon 2008: Conference: Information for Authors

Here, you will find information for speakers, room assignments, speaker registration, and a wealth of other information to make your experience at the Broadband World Forum Americas as productive as possible.

Please check back often as information will be updated on a regular basis.

Information in this section includes the following:

- IEC Contacts
- Room Setup
- On-Site Speaker Preparation Room
- Paper Deadline
- Presentation Guidelines
- Day of Presentation
- Session Format
- Registration and On-Site Check-In
- Speaker Substitutions
- Paper Award Info
- Room Locations

IEC Contacts

Christine Paplaczyk Exhibit and Sponsorship Opportunities Phone: +1-312-559-4616 cpaplaczyk@iec.org	Greg Kinley Operations Phone: +1-312-559-3303 gkinley@iec.org	Barry Sullivan Content Development Phone: +1-312-559-3302 bsullivan@iec.org
Caitlin Thomson Speaking Opportunities Phone: +1-312-559-4137 cthomson@iec.org	Kim Simpao Event Marketing Phone: +1-312-559-3657 ksimpao@iec.org	Michelle Klein Exhibitor Marketing Phone: +1-312-559-3861 mklein@iec.org
Lisa Reyes Media Relations and Public Relations Phone: +1-312-559-3325 lreyes@iec.org	Dan Opine Exhibitor and Sponsorship Fulfillment Phone: +1-312-559-3731 dopine@iec.org	Kim Simpao Associate Sponsor Relations Phone: +1-312-559-3657 ksimpao@iec.org

Room Setup Session rooms are equipped with the following:

LCD projector
Cabling
Screen
Microphone at speaker head table and podium
Tent cards with names of speakers placed at speaker seating
Head table for all speakers placed at the front of the room

If you have special AV needs in addition to those included in the standard room setup, please contact Caitlin Thomson at cthomson@iec.org.

Please note: Laptop computers are not provided in the rooms.

On-Site Speaker Preparation Room A dedicated speaker preparation room will be available to all speakers in Room 211. Speakers are welcome to use the speaker preparation room for on-site preparation meetings with their panelists.

Paper Deadline Deadline: All papers are due by November 16, 2007.

Papers should be prepared using the formatting guidelines and sent to Caitlin Thomson at cthomson@iec.org.

Formatting guidelines PDF

Formatting guidelines MS Word

Presentation Guidelines The following are some helpful tips in regard to producing your presentation:

Presentations are to be noncommercial.
The IEC does not have a PowerPoint template; feel free to use your own.
Avoid too much content on one slide, as attendee feedback has voiced negative comments with regard to this.
Keep in mind that presentations are meant to provide the same information contained in the paper itself but in a condensed and visually acceptable format.
We encourage authors to send their presentations for posting on the DesignCon Web site. Please send to cthomson@iec.org by January 10, 2008.

Day of Presentation The day of your presentation, please bring your laptop computer, as laptops are not provided in session rooms. We suggest loading all presentations on one laptop for easy transition from one speaker to the next.

Session Format

Paper sessions are 40 minutes long.
Speakers should prepare 30-minute presentations, leaving 10 minutes for questions and discussion.

Registration and On-Site Check-In Registration: Chairpersons and speakers should register for DesignCon using a special speakers' on-line registration form offering a selection of conference packages. Speakers and authors for DesignCon 2008 are given complimentary registration for the full four-day program.

On-Site Check-In: Once you arrive at the Santa Clara Convention Center, speakers are asked to check in at the DesignCon registration desk to pick up name badges and other credentials.

Speaker Substitutions Inform IEC staff Caitlin Thomson and/or Barry Sullivan of any speaker substitutions.

If substitutions arise at the event, go to an Advance Registration counter and let the staff member attending the desk know who you are replacing.

Paper Award Info DesignCon Paper Awards recognize outstanding contributions to the educational goals of the DesignCon program. Papers are judged both on the merits of the written document and on the quality of their presentation at DesignCon events.

The awards serve to acknowledge the authors who receive them as leading practitioners in semiconductor and electronic design. The awards also provide incentive to authors to produce high-quality DesignCon papers and present them in a lucid and compelling manner.

Paper Review

The first step of the selection process is a review of the full-length papers accepted for the DesignCon 2008 technical program. Members of the DesignCon 2008 Technical Program Committee will receive the full-length papers for the tracks they reviewed. They will send their choices for the top papers in the track to Barry Sullivan, DesignCon program director. Finalists for each track will be selected based on the votes from the reviewers.

Papers are judged along the following dimensions, listed in order of importance:

Quality-An award-quality paper should be well organized and easily understood. This is a straightforward area to judge, especially on a relative basis.
Relevance-The paper should be highly relevant to the interests of the DesignCon audience and the track topic in particular.
Impact-Award papers should make a substantial contribution to the educational mission of DesignCon. Papers reporting on important results, methodologies, or case studies of special significance should be recognized.
Originality-This area requires special note. Keeping in mind the goal of providing a high-quality educational program for practicing engineers, it is easy to see that a report on a new design methodology or a case study for an innovative design has great educational value. However, an outstanding paper on a "classical" topic can be an award candidate, and papers of this sort should also be viewed favorably.
Commercial content-Another area deserving special mention. It is acceptable to use a product in a design case study or as a proof of concept for a design methodology, and many of the papers the DesignCon audience views most favorably do just that. However, we also know that the audience responds most negatively to anything that comes across as a product pitch. A good case study that uses a real product in an appropriate manner to demonstrate feasibility or illustrate a concept should be considered favorably.

Judging Presentations

Effective presentations add significantly to the educational value of the DesignCon technical program. While selection as a finalist for a DesignCon Paper Award is a notable achievement in itself, award winners will be chosen from among the finalists based on the quality of their presentations. The same dimensions for evaluation of the written papers — quality, relevance, originality, and commercial content — apply here as well, although quality will be the primary criterion. Judges are recruited from the DesignCon 2008 Technical Program Committee to ensure adequate coverage of the award areas listed above.

Room Locations

Monday, February 4
TIME	SESSION	LOCATION
9:00 – 12:00	TF-MA1 \| Tutorial The Great EDA Cover-Up: Coverage Metrics Explained	Ballroom F
	TF-MA2 \| Tutorial Advances in Gigabit Channel Measurement-Based Characterization and Simulation	Ballroom G
	TF-MA3 \| Tutorial Chip, PCB, and Connector Technologies for Meeting Today's and Tomorrow's 10+Gb Signaling Requirements — a Report on Current Trends and Future Road Maps	Ballroom H
	TF-MA4 \| Tutorial Computational Electromagnetics: From Maxwell's Equations to Signal Integrity and System Design	Room 203/204
	TF-MA5 \| Tutorial Tools for Reducing the Hidden Costs in the IP Supply Ecosystem	Ballroom E
12:30 – 1:00	Monday Keynote Address	Great America Ballroom
1:30 – 4:30	TF-MP1 \| Tutorial Design of High-Performance Adaptive FIR Filters Using FPGA	Ballroom E
	TF-MP2 \| Tutorial Developing Interoperable Algorithmic Models Quickly — A Tutorial	Ballroom G
	TF-MP3 \| Tutorial Design and Verification for Jitter and High-Speed I/Os at Multiple Gbps	Ballroom H
	TF-MP4 \| Tutorial AdvancedTCA (ATCA) Platform Design and Applications: A New Day in Scalable Telecom System Deployment	Ballroom F
	TF-MP5 \| Tutorial The ABCs of System-Level Design	Room 203/204
4:45 – 6:00	Technical Panel Is Coverage the Best Metric for Verification Closure?	Ballroom E
	Technical Panel Challenges in Verification and Compliance of Serial Data Technologies	Ballroom F, G
	Technical Panel Understanding the Impact of 100G Ethernet	Ballroom H
Tuesday, February 5
TIME	SESSION	LOCATION
8:30 – 9:10	1-TA1 How to Quickly Create Complicated Message Sequence Charts Automatically without Spending Money on Software	Room 209
	5-TA1 Utilization of Buried Capacitance(TM) — A Case Study	Ballroom F
	7-TA1 The Impact of Common Mode Currents and Interconnect Inductance on the Signal Quality of Differential Signals in Multi-Board PCB Systems	Great America Ballroom J
	8-TA1 Analysis of Crosstalk Effects on Jitter in Transceivers	Great America Ballroom K
	10-TA1 Impact of PCB Laminate Dimensions on Suppressing Modal Resonances	Ballroom G
	12-TA1 Challenges and Solutions for Removing Fixture Effects in Multiport Measurements	Ballroom H
	15-TA1 Is Congress Killing Innovation?	Room 210
8:30 – 10:00	Business Forum Panel Managing Unit Costs: Methodologies and Processes to Lower Overall Chip Costs	Room 203/204
9:20 – 10:00	1-TA2 Designing and Verifying Ratio Synchronous Clocks (RSC) for High-Performance Low-Power Processors	Room 209
	5-TA2 Application of Foldy-Lax Multiple Scattering Method to Via Analysis in Multilayered Printed Circuit Board	Ballroom F
	7-TA2 Data Mining 12-Port S-Parameters	Great America Ballroom J
	8-TA2 Modeling a Phase Interpolator as a Delta-Sigma A/D converter	Great America Ballroom K
	9-TA2 Design Considerations in High-Speed SerDes (25 Gbps)	Ballroom E
	10-TA2 High Bandwidth Modeling and Simulation of SSO Effects on Single-Ended Switching Performance of Complex FPGA System Designs	Ballroom G
	12-TA2 Broadband Resonant-Plate Permittivity Measurement Technique for Printed Wiring Boards Aided by Electromagnetic Simulations	Ballroom H
	15-TA2 Case Study Using the VSIA QIP to Evaluate Internally Developed Information Property	Room 210
10:15 – 10:55	1-TA3 ESL Driven Instrumentation Interfaces	Room 209
	2-TA3 Hope Is Not a (Verification) Strategy — Coverage Model-Driven Functional Scenario Generation	Ballroom E
	5-TA3 Modeling Issues and Possible Solutions in the Design of High-Speed Systems with Signals at 20 Gbps	Ballroom F
	7-TA3 Demonstration of SerDes Modeling Using the Algorithmic Model Interface (AMI) Standard	Great America Ballroom J
	8-TA3 Characterization of Gaussian Noise Sources	Great America Ballroom K
	10-TA3 Analyzing the Impact of Simultaneous Switching Noise on System Margin in Gigabit Single-Ended Memory Systems	Ballroom G
	13-TA3 Study of Fundamental Limit and Packaging Technology Solutions for 40 Gbps Transceiver Package Design	Ballroom H
	15-TA3 Lifecycle Cost Is a DIME - How to Make Build/Buy Decisions	Room 210
10:15 – 11:45	Business Forum Panel Executive Views on the Turbulent FPGA Landscape	Room 203/204
11:05 – 11:45	1-TA4 A Reset Control Apparatus for PLL Power-Up Sequence and Auto-Synchronization	Room 209
	2-TA4 Bridging Block-Level to Top-Level CDC Verification: Hierarchical CDC Verification	Ballroom E
	5-TA4 Solutions for Causal Modeling and a Technique for Measuring Causal, Broadband Dielectric Properties	Ballroom F
	7-TA4 BladeServer 10 Gbps Ethernet Backplane Design with Equalization Using Statistical Channel Analysis	Great America Ballroom J
	8-TA4 Crosstalk Measurement, Extraction, and Validation in 10 Gbps Serial Systems	Great America Ballroom K
	10-TA4 Pushing the Envelope without Tears: An Advanced Power Delivery Solution	Ballroom G
	13-TA4 Issues of Frequency Content of S-Parameter Data for High-Speed Channel Evaluation	Ballroom H
	15-TA4 ASIC 2-0	Room 210
12:00 – 12:30	Tuesday Keynote Address	Theater
2:00 – 2:40	1-TP1 Design and Application of Embedded Waveform Viewing Technology for Integrated Circuits	Room 209
	2-TP1 A Python-Based SoC Validation and Test Environment	Ballroom E
	5-TP1 ATE Interconnect Performance to 43 Gbps Using Advanced PCB Materials	Ballroom F
	7-TP1 Strategies for Coping with Nonlinear and Time Variant Behavior for High-Speed Serial Buffer Modeling	Great America Ballroom J
	8-TP1 A Novel Approach for Characterizing Pulse Width Shrinkage in High-Speed Digital Communications Systems	Great America Ballroom K
	10-TP1 Using Full Wave Solvers for Practical Analysis of Capacitor Mounting Structures	Ballroom G
	13-TP1 Validation Methods for S-Parameter Measurement-Based Models of Differential Transmission Lines	Ballroom H
	15-TP1 BDU — A Complexity Measure for a Board Design Project	Room 210
2:00 – 3:30	Business Forum Panel Ecosystem Environment for Starting a Semiconductor Company	Room 203/204
2:50 – 3:30	1-TP2 Methods for Configurable Hardware Design	Room 209
	2-TP2 Sources of Non-Determinism in Microprocessors	Ballroom E
	4-TP2 Simulations and Characterizations for GHz On-Chip Power Delivery Network (PDN)	Ballroom F
	7-TP2 Multi-Gbps Serial Channel Design Using a Hybrid Measurement and Simulation Platform	Great America Ballroom J
	8-TP2 Exploration of Deterministic Jitter Distributions	Great America Ballroom K
	11-TP2 Mode Conversion and EMI Performance of Shielded Cable Assemblies for 10 Gbps Data Transmission	Ballroom G
	13-TP2 A New Test Fixture Crosstalk De-Embedding Technique Using Time-Domain Gating	Ballroom H
	14-TP2 Modeling FPGA Current Waveform and Spectrum and PDN Noise Estimation	Room 210
3:45 – 5:00	Technical Panel ASIC Verification	Ballroom F
	Technical Panel High-Speed PCB Traces: What Is Their Real Performance?	Ballroom G
	Technical Panel The Call for Industry Research on Next-Generation Electrical Signaling	Ballroom H
	Business Forum Panel Emerging Markets — Tackling Market Opportunities in India	Room 203/204
Wednesday, February 6
TIME	SESSION	LOCATION
8:45 – 9:25	1-WA1 Multimedia Application Specific Engine Design Using High-Level Synthesis	Room 209
	3-WA1 Using Programmable Logic for Receiver Offset and Yield Enhancement	Room 210
	6-WA1 A Fast Algorithm to Instantly Predict FPGA SSN for Various I/O Pin Assignments	Ballroom E
	7-WA1 The Need for Impulse Response Models and an Accurate Method for Impulse Generation from Band-Limited S-Parameters	Great America Ballroom J
	9-WA1 Semi-Analytic Performance of NRZ/PAM4/PR2 Modulation across 8.5-25 Gbps Backplanes with Analog Equalization	Great America Ballroom K
	11-WA1 Heat Sink Design Flow for EMC	Ballroom F
	12-WA1 A Jitter Estimation Method for Cascaded, Programmable Phase-Locked Loops	Ballroom G
	14-WA1 The Future of Multi-Clock Systems	Ballroom H
8:45 – 10:20	Business Forum Panel Refining or Redefining the Analog Design Sign-Off Flow	Room 203/204
9:40 – 10:20	1-WA2 Evaluating Embedded Non-Volatile Memory for 65 nm and Beyond	Room 209
	3_WA2 Packaging DfM into Design Service	Room 210
	6-WA2 Challenges in Implementing DDR3 Memory Interface on PCB Systems - A Methodology for Interfacing DDR3 SDRAM DIMM to an FPGA	Ballroom E
	7_WA2 Aggregation of Crosstalk in Backplanes	Great America Ballroom J
	9-WA2 Pre-Cursor ISI Cancellation	Great America Ballroom K
	11_WA2 Loaded Parallel Stub Common Mode Filter	Ballroom F
	12-WA2 50 GHz End Launch Connector Test Boards: the Description of the Development of Coax to Grounded Coplanar Launches and Through Lines on 30 mil Rogers 4350 Material with Comparison to Microstrip	Ballroom G
	14_WA2 Interface Based Design Concepts for IC, PKG, PCB Co-Design	Ballroom H
10:30 – 11:45	Plenary Panel Navigating the ASIC Manufacturing Landscape	Theater
12:00 – 12:30	Keynote Address	Theater
2:00 – 2:40	2-WP1 How to Find if My Checker Is Complete and Exhaustive — A Set of Guidelines Using Systemverilog and Memory Controller Example	Room 209
	4-WP1 Process and Temperature Variations on Electrical Parameters of Wire-Bond BGA Packages: An Impact Analysis Using Simulation-Based DOE Methodology	Room 210
	6-WP1 Counting the Picoseconds: Integrating Timing, Signal, and Power Integrity Analysis	Ballroom E
	8-WP1 PCI Express Timing Margins	Great America Ballroom J
	9-WP1 Half-Rate Decision-Feedback Equalization — Di-Bit Response Analysis & Evaluation	Great America Ballroom K
	11-WP1 Cable EMI Characterization Using a Reverberation Chamber	Ballroom F
	12-WP1 High-Speed Serial Interconnect Imbalance	Ballroom G
	14-WP1 Efficient Modeling and Design Optimization Methodology for Integrated Power and Signal Distribution in Digital Systems	Ballroom H
2:00 – 3:30	Business Forum Panel Where Is the ROI for DFM?	Room 203/204
	2-WP2 Mixed-Signal Integration: Functional Verification in the Presence of Linear Analog Components	Room 209
	4-WP2 FPGA I/O Timing Variations Due to Simultaneous Switching Outputs	Room 210
	6-WP2 Study of Signal and Power Integrity Challenges in High-Speed Memory I/O Designs Using Single-Ended Signaling Schemes	Ballroom E
	8-WP2 A Systematic Approach to Solving Clock Synthesis and Clock Recovery Problems in High-Data-Rate Serial Bus Systems	Great America Ballroom J
	9-WP2 Multilevel Signaling in High-Density, High-Speed Electrical Links	Great America Ballroom K
	11-WP2 EMI Shielding of Cable Assemblies	Ballroom F
	12-WP2 Characterization Methodology for High-Density Microwave Fixtures	Ballroom G
	14-WP2 Techniques for Co-Design of the Power Supply Chain from IC to Printed Circuit Board	Ballroom H
3:45 – 5:00	Technical Panel IP Standards — Where Do We Go from Here?	Ballroom F
	Technical Panel Advanced High-Speed Serial Channel Metrics	Ballroom G
	Technical Panel Package Extraction, Modeling, and Simulation in IC-Packaging-Board Design	Ballroom H
	Business Forum Panel Designing a More Fulfilling Career	Room 203/204
Thursday, February 7
TIME	SESSION	LOCATION
9:00 – 9:40	1-THA1 On-Chip Instrumentation for In-System IP Validation of a 6 Gbps Serial ATA Platform Device	Ballroom E
	2-THA1 Visual Data Analysis Approach to Design Verification	Ballroom F
	7-THA1 In Situ Characterization of High-Speed Signaling Systems with On-Chip Measurements	Ballroom G
	12-THA1 High-Speed Probe Interconnect Techniques	Ballroom H
9:50 – 10:30	1-THA2 HW/SW Partitioning Tradeoffs in 3G & WiMAX Wireless Base Stations	Ballroom E
	2-THA2 Formal Verification Flow in FPGA Designs	Ballroom F
	7-THA2 Performance Limitations of Backplane Links at 6 Gbps and Above	Ballroom G
	12-THA2 Performance at the DUT: Techniques for Evaluating the Performance of an ATE System at the Device under Test Socket	Ballroom H
10:40 – 11:20	1-THA3 Transaction Level Assertions in an Interface Definition Language	Ballroom E
	7-THA3 A Design of Experiments for Gigabit Serial Backplane Channels	Ballroom G
	12-THA3 Frequency Domain Calibration: A Practical Approach for the Serial Data Designer	Ballroom H

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