DesignCon 2008: Conference: Schedule

Congratulations to the DesignCon Paper Award Winners

DesignCon Paper Awards recognize outstanding contributions to the educational goals of the DesignCon program. Papers are judged both on the merits of the written document and on the quality of their presentation at DesignCon 2008.

Chip-Level Design Category

1-TP1	Design and Application of Embedded Waveform Viewing Technology for Integrated Circuits Gary McCormack, Vitesse Semiconductor Eric Sweetman, Vitesse Semiconductor Ian Kyles, Vitesse Semiconductor
4-TP2	Simulation and Characterization of GHz On-Chip Power Delivery Network (PDN) Vishram S. Pandit, Senior Engineer, Intel Corporation Woong Hwan Ryu, Senior Staff Engineer, Intel Corporation Kirupa Pushparaj, Intel Corporation Sankalp Ramanujam, Intel Corporation Farag Fattouh, Intel Corporation
Functional and Performance Verification Category
2-TA3	Hope Is Not a (Verification) Strategy — Coverage Model Driven Functional Scenario Generation Adnan Hamid, Chief Executive Officer, Breker Verification
Board and System Design Category
5-TA4	Solutions for Causal Modeling and a Technique for Measuring Causal, Broadband Dielectric Properties Chad Morgan, Member of Technical Staff, Tyco Electronics
10-TA3	Analyzing the Impact of Simultaneous Switching Noise on System Margin in Gigabit Single-Ended Memory Systems Ralf Schmitt, Senior Engineering Manager, Rambus Joong-Ho Kim, Senior Member of Technical Staff, Rambus Woopoung Kim, Senior Member of Technical Staff, Rambus Dan Oh, Engineering Manager, Rambus June Feng, Senior Member of Technical Staff, Rambus Chuck Yuan, Signal Integrity Engineer, Rambus Lei Luo, Rambus John Wilson, Rambus
Interconnect Design Category
6-WP2	Study of Signal and Power Integrity Challenges in High-Speed Memory I/O Designs Using Single-Ended Signaling Schemes Kyung Suk (Dan) Oh, Senior Engineering Manager, Rambus Woopoung Kim, Rambus Joong-Ho Kim, Rambus John Wilson, Rambus Ralf Schmitt, Rambus Chuck Yuan, Rambus Lei Luo, Rambus Jade Kizer, Rambus John Eble, Rambus Fred Ware, Rambus
7-WA1	The Need for Impulse Response Models and an Accurate Method for Impulse Generation from Band-Limited S-Parameters Fangyi Rao, Senior Software Development Engineer, Agilent Technologies Chad Morgan, Member of Technical Staff, Tyco Electronics Sanjeev Gupta, Signal Integrity Specialist, Agilent Technologies Vuk Borich, Operating Manager, Agilent Technologies
High-Speed and RF Design Category
9-WP2	Multi-Level Signaling in High-Density, High-Speed Electrical Links Dong Kam, Postdoctoral Researcher, IBM T. J. Watson Research Center Troy Beukema, Research Staff Member, IBM Young Kwark, Research Staff Member, IBM Lei Shan, Research Staff Member, IBM Xiaoxiong Gu, Research Staff Member, IBM Petar Pepeljugoski, Research Staff Member, IBM T. J. Watson Research Center Mark Ritter, Research Manager, IBM T. J. Watson Research Center
11-TP2	Mode Conversion and EMI Performance of Shielded Cable Assemblies for 10 Gbps Data Transmission Jim Nadolny, Senior SI/EMI Engineer, Samtec Julian Ferry, High Speed Engineering Manager, Samtec Cesar Arroyo, Senior Electronics Technician, Samtec
Test and Measurement Category
12-THA2	Performance at the DUT: Techniques for Evaluating the Performance of an ATE System at the Device under Test Socket Heidi Barnes, Senior Consultant, Verigy Jose Moreira, Senior Application Consultant, Verigy Michael Comai, Senior Product Engineer, Advanced Micro Devices Abraham Islas, Senior Product Engineer, Advanced Micro Devices Francisco Tamayo-Broes, Product Development Engineer, Advanced Micro Devices Mike Resso, Signal Integrity Measurement Specialist, Agilent Technologies Antonio Ciccomancini Scogna, Application Engineer, CST of America Orlando Bell, Vice President of Engineering, GigaTest Labs Ming Tsai, Amalfi Semiconductor