1. Chip-Level Architectural and Functional Design Sample topics System architectures and partitioning Specification, constraints, and design estimation Low-power strategies Performance and power analysis/optimization Performance power throttling On-chip interconnects Clock and reset strategies Multi-abstraction modeling and languages Tools and tool flows for design IP reuse and quality metrics IP/memory integration (ASSPs, MCMs, SoCs) Hardware/software co-design Hardware-dependent software Embedded processor design issues Design for test/verification (DFT, DFV) On-chip debug design strategies Synthesis, timing budgeting, and timing closure Logic synthesis for VLSI design Electronic system level (ESL) design Platform-based design 2. Functional and Performance Verification Sample topics Verification planning Reuse methodology and verification IP Assertion-based verification Verification progress assessment Coverage measurement and analysis Coverage of formal analysis Coverage-directed verification Fault observability analysis Practical use of formal/semiformal methods Modeling for verification System-level verification HW/SW co-verification Hardware-based verification Mixed-signal verification Application performance verification Verification flow engineering Verification languages Transaction verification and scenario identification 3. Chip-Level Physical Design and DFM Sample topics Bare-die applications Chip-design methodologies Clock-tree designs Design for manufacturing/yield (DFM, DFY) Design margining Simulation techniques and methodology Statistical modeling Variation-tolerant design Yield analysis and reliability Design-rule checking (DRC), design closure Fault tolerance, redundancy Floor planning High-speed I/O design Low-power implementation Mixed-signal circuits On-chip instrumentation and measurement On-die testability Power analysis and distribution Programmable fabrics Radiation-hardened circuit approaches Resolution enhancement and mask data preparation 4. Chip-Level Electrical and Package Design Sample topics Buffer modeling Ceramic versus organic Dynamic power scaling EMI immunity/susceptibility Electrostatic discharge (ESD) protection Grounding strategies High-speed signaling, I/O interoperability I/O SSO (simultaneous switching of output) Integrated optical links Merging of chip design and package design Mixed-signal design Multi-voltage design Package modeling and measurement Power grid modeling and analysis Power integrity and management Signal integrity, crosstalk System-in-package (SiP), multi-chip package (MCP) design Thermal management Timing closure 5. PCB and Passive Component Technology Sample topics Advanced conductive and dielectric materials Impact of low copper surface roughness Advanced laminate and PCB processing High aspect-ratio vias Microvias, RF vias, and thermal vias Interlayer connectivity alternatives Fine registration improvements Backdrilling methods and effects Electrical and mechanical co-design EM modeling of PCB traces and vias Embedded devices Passive and active devices Embedded optical channels Power delivery Fabrication: cost versus performance Rigid-flex and multilayer flex circuit design and manufacturing Halogen-free materials Impact of lead-free materials and processes Manufacturing impact on electrical properties Materials modeling (non-homogeneous) Sockets and connectors Thermal characterization Via pin-field design 6. High-Speed Parallel Interface Design Sample topics System/FPGA/ASIC timing closure Timing analysis methodologies Statistical timing, bit-error-rate analysis Designing with dynamically aligned timing Signal integrity simulation High speed I/O modeling Crosstalk Modeling and incorporating effects of SSO Signal slew rate and impact on timing Designing with impedance-controlled buffers/on-die termination Differential versus single-ended signaling Performance versus power versus signal integrity Rules-based design Developing and managing high-speed layout rules Standards-based design (e.g., DDR2/3, HyperTransport 3.0, PCI-X, SPI 4.2) Developing standard design specifications and budgets Design margin versus complexity versus cost Lab measurements and correlation Managing measurement based uncertainty Optimizing training patterns and test sequences High-speed cable design, analysis, and modeling Interconnect signal-conditioning techniques

7. Multi-Gigabit Serial Interconnects Sample topics Backplane and cable interconnect Backplane and cable signal conditioning Copper versus fiber tradeoffs Design verification and validation Ethernet architectures Loss and timing budgets Physical modeling and simulation Signal integrity for backplanes and cables SerDes design techniques System interconnect architecture Switch-fabric architectures 8. High-Speed Timing, Jitter, and Noise Sample topics Bit-error-ratio analysis and measurement Embedded clock buses Inter-symbol interference Jitter simulation, analysis, and measurement Multi-gigabit signal integrity Signal conditioning Time/frequency domain translation Timing closure 9. High-Speed Signal Processing, Equalization and Coding Sample topics Active/passive pre-emphasis and equalization Adaptive tap optimization Digital pre-emphasis and equalization Error-correction coding Eye diagram compliance testing Measurement verification Multi-level signaling Signal detection algorithms Signal modeling and measurement Simulation algorithms 10. Power Integrity and Power-Aware Design Sample topics DC-DC converter characteristics Silicon power measurement and correlation Multi-voltage and power-gating design Power supply design, dynamic response Power-aware architecting Signal/power integrity co-design Advanced power management Power integrity optimization Charge delivery analysis Simultaneous switching noise (SSN) suppression IR-drop analysis 11. Electromagnetic Compatibility and Interference Sample topics EMI radiation and suppression ESD compliance and testing Mixed-signal design issues Near-field coupling & crosstalk Noise characterization & containment Emissions & interference modeling Shielding & package design Signal encoding & emission reduction EMI issues with differential signaling 12. Test Fixturing and Measurement Methodology Sample topics Metrology of the measurements Instrumentation performance and measurement errors Resolution and sensitivity Algorithms for accuracy and resolution improvement Calibration and accuracy Methods and system architecture ATE and subsystems Automatic test-pattern generation Fluctuations, noise, jitter transformation Active/passive device measurement methods Analog, mixed signal, and RF testing SoC testing: memory, IP Package, connector, board testing Testing gigabit I/O Fixture de-embedding methodologies Signal integrity and fixture de-embedding 3D-solver and measure-based test fixture design methods Backplane/pin signal integrity Chip/package/board/system measurement methods Separation effects of decoupling, power, signal integrity Silicon characterization/de-embedding Probing and on-wafer measurements Advanced measurements and DFM Yield analysis and yield enhancement Fault modeling and failure analysis Prototyping Test coverage 13. RF and Signal Integrity Sample topics RF chip/package/board design and simulation Nonlinear RF circuit simulation with coupled chip/package/board parasitics RF module EMI/EMC Portable wireless device system signal integrity Portable wireless device receiver de-sense Portable wireless device power distribution RF system noise Digital-analog system integration Common mode radiation Intermodulation distortion, RF leakage, noise figure, DC offset in radio circuits caused by chip/package/board parasitics RF and EMI system susceptibility RF and system EMC radiation Minimizing crosstalk in high-speed channels 14. Chip/Package/Board/System Co-Design Sample topics Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications) PCB/package/chip/device power modeling End-to-end link modeling Pin-out optimization Signal fan-out Simultaneous switching noise Sub-system interaction System integration challenges System-level de-coupling strategy System-level power and signal integrity System noise modeling and mitigation 15. Business and Engineering Impacts Sample topics Business impact of engineering decisions Engineering impact of business decisions Components of reusable IP Cost versus performance tradeoffs Designing for time to market Fabless design business issues Globalization impacts IP integration into products and systems Make versus buy decision process Market constraints on design Outsourcing, legal, and personnel issues Packaging selections Partner selection process and methods Product cycles and versioning Product/component costing analysis methods Reusable IP management (infrastructures) Reuse decision metrics Strategic and tactical balance Third-party IP business and legal models Tradeoffs due to resources Venture start-up process