This popular series of business sessions provides access to leaders in the design process who offer their strategies for thriving in this fast-paced electronics industry. Executives and senior managers will conduct panel discussions that complement technical paper sessions and add insights on current issues. Presented over two days, the Business Forum is open to attendees who buy a conference package.

Business Forum sessions include:

Tuesday, February 5
8:30 am – 10:00 am	Business Forum Panel Managing Unit Costs: Methodologies and Processes to Lower Overall Chip Costs
	Chairperson: Adam Traidman President Chip Estimate Corporation
10:15 am – 11:45 am	Business Forum Panel Executive Views on the Turbulent FPGA Landscape
	Chairperson: Simon Bloch General Manager, Design and Synthesis Division Mentor Graphics
2:00 pm – 3:30 pm	Business Forum Panel Ecosystem Environment for Starting a Semiconductor Company
	Chairperson: Steve Szirom President of Online Information Services InsideChips
3:45 pm – 5:00 pm	Business Forum Panel Emerging Markets — Tackling Market Opportunities in India
	Chairperson: Jaswinder S. Ahuja Corporate Vice President, Managing Director Cadence Design Systems

Wednesday, February 6
8:45 am – 10:20 am	Business Forum Panel Refining or Reducing the Analog Design Sign-Off Flow
	Chairperson: Gary Smith Founder and Chief Analyst Gary Smith EDA
10:30 am – 11:45 am	Plenary Panel Navigating the ASIC Manufacturing Landscape
	Chairperson: Kazu Yamada Vice President and General Manager, Custom SOC Solutions Business Unit Gary Smith EDA
2:00 pm – 3:30 pm	Business Forum Panel Where Is the ROI for DFM?
	Chairperson: Mike Santarini Senior Editor EDN
3:45 pm – 5:00 pm	Business Forum Panel Designing a More Fulfilling Career
	Chairperson: John Epperheimer Partner St. Charles Consulting Group