Design for manufacturability (DFM) has struggled to meet expectations because of the increasing complexity of designs, stringent design rules, limited tools, and designer resistance to fully adopt DFM. But DFM is not an option at 45 nm and below-it will be a requirement as consumer electronics drive the industry's demand for more speed and functionality at lower cost. Collaboration will help, but broader partnerships that span industry segments-involving designers, photomask makers, equipment suppliers, IC fabs, and foundries-are necessary to deliver DFM's potential and produce the return on investment needed to justify increasing costs.

This panel explores the major challenges to implementing DFM, including what are the actual costs of implementing DFM and how to measure the return on investment.

Issues/responses to be covered include the following:

• Overcoming productivity problems for designers or simplifying DFM for designers
• Developing more robust tools
• PSM/OPC enhancement
• Rules-based solutions versus model-based solutions
• Incremental steps versus rapid evolution
• Communication across the industry
• Are foundries doing enough to advance DFM?
• Would consolidation in the EDA sector help?

Mike Santarini Senior Editor EDN

Mr. Santarini covers EDA, IP, ASICs, programmable logic, and memory. He joined EDN in January 2005, after seven years at EE Times, where he specialized in reporting on IC and system-design tools and methodologies, covering the EDA and IP industries and their impact on FPGA, ASIC, and PCB design. In 2003, Mr. Santarini won one of two exclusive feature awards at CMP Media for an expose on a failed takeover attempt of MIPS Technologies by licensees. Before joining EE Times in July 1997, he was an associate editor at Integrated System Design magazine, which he joined in 1995. Mr. Santarini holds a B.A. in English from Santa Clara University.

Luigi Capodieci Fellow, RET/OPC Automation and DFM Advanced Micro Devices

Dr. Capodieci works on optical proximity correction, phase shift masks, imaging simulations, and lithography R&D. At AMD he pioneered the field of design for manufacturability (DFM), merging physical design practices with rigorous printability modeling. He is currently a fellow at AMD, coordinating advanced OPC and DFM automation for 45 nm, 32 nm, and 22 nm technology nodes. Dr. Capodieci received his doctorate in electronic engineering and computer science from the University of Bologna in Italy in 1988 and a Ph.D. in electrical engineering from the University of Wisconsin-Madison in 1996.

Nitin Deo Senior Director, DFM Marketing Cadence

Mr. Deo has a unique background, having worked in design, product marketing, sales, and business development. Before joining Clear Shape, Nitin was senior vice president of marketing and business development at Ponte. Mr. Deo was marketing executive at Moscape. After the pre-IPO acquisition of Moscape by Magma, he became VP and GM for Japan operations for three years, leading Magma's highly successful initial foray into Japan. He was also VP of marketing and business development at Magma. He worked at Fujitsu and Philips and was at Synopsys for five years as group director of marketing and business development. He has a B.S.E.E. from Mysore, an M.S.E.E. from Virginia Tech, and an M.B.A. from San Jose.

Ross Hirschi Director, DFM Freescale Semiconductor

Mr. Hirschi has 23 years of experience in PC board and SoC design. Currently, he is responsible for cultivating a DFM-aware culture and providing DFM tools and methods to the design community. Prior to his current role, Mr. Hirschi held multiple positions in design management, including director of Freescale's Japan Design Center in Sendai, Japan, for three years. He holds a B.A. in electrical engineering from Brigham Young University and an M.B.A. degree from Texas Christian University.

Franklin Kalk Executive Vice President and Chief Technology Officer Toppan Photomasks, Inc.

Dr. Kalk leads Toppan Photomasks' global research-and-development programs, supporting customers' technology road maps. Dr. Kalk joined DuPont Photomasks in 1992 and has led several tool and material development programs. For the past several years, Dr. Kalk has focused on photomask resolution-enhancement technology issues and led company-wide programs aimed at improving the quality and yield of photomask products. Prior to joining DuPont Photomasks, he held a number of engineering and research positions in the electronics group of E.I. duPont de Nemours & Co. He began his career at Storage Technology Corp. Dr. Kalk holds 16 U.S. patents and has published numerous technical papers. He holds a doctorate in optics from University of Rochester and a bachelor's degree in physics from Emory University.

Edward Wan Senior Director of Design Services Marketing TSMC North America

Mr. Wan is currently the senior director of design services marketing of TSMC North America. Before joining TSMC, Mr. Wan was CEO of Spike Technologies, a leading chip-design services company in Milpitas, California. Prior to Spike Technologies, he was vice president of worldwide field engineering of United Microelectronics Corporation, where he directed the internal design activities as well as the external network of library, IP, and design services providers. Mr. Wan also held the position vice president at Cadence and vice president of engineering at LSI Logic, where he managed LSI Logic's North American design centers. He started his technology career as a circuit designer, product engineer, and applications engineer at Signetics Corporation. Mr. Wan has a B.S.E.E. from UC Berkeley.