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Conference ScheduleInfoVault
Business Forum Panel
Refining or re-defining the Analog Design Sign-Off Flow
Wednesday, February 6 | 8:45 am – 10:20 am
Consumer applications are spurring the need for faster and more accurate design cycles for mixed-signal chips to go into end products such as game and music players and cell phones. As the complexity of these end products increases, the need for mixed-signal chips to go into these applications increases.

Chairperson
Gary Smith
Founder and Chief Analyst
Gary Smith EDA
Prior to his current position, Mr. Smith was the managing vice president and chief analyst of the Electronic Design Automation Service at the Design and Engineering Cluster at Gartner Dataquest. While at LSI Logic, Mr. Smith became an evangelist for the RT-level design methodology. He is a current member of the Design TWG for the International Semiconductor Road Map (ITRS), is the editorial chair of the IEEE Design Automation Technical Committee (DATC), and serves on the DAC Strategic Committee. Mr. Smith earned his Bachelor of Science degree in engineering from the United States Naval Academy.

Speakers
Sandipan Bhanot
President and CEO
Knowlent Corporation
Mr. Bhanot is responsible for setting the overall company direction and enabling the successful industry adoption of Knowlent products. Before founding Knowlent, he was the senior product manager for the Silicon Ensemble product line at Cadence Design Systems. Prior to Cadence, Mr. Bhanot worked at Synopsys and SCL. He holds an M.B.A. from the Haas School of Business at UC Berkeley and a B.S. in computer science from Institute of Technology in Varanasi, India.

Robert Dobkin
Vice President, Engineering and Chief Technical Officer
Linear Technology Corp.
Mr. Dobkin is a founder and chief technical officer of Linear Technology Corporation. At Linear he was responsible for all new product development until 1999. Prior to founding Linear Technology in 1981, Mr. Dobkin was director of Advanced Circuit Development at National Semiconductor for 11 years. He has been intimately involved in the development of high-performance linear integrated circuits for more than 30 years and has generated many industry-standard circuits. He attended the Massachusetts Institute of Technology.

Steve Lewis
Product Marketing Director
Cadence
Mr. Lewis is an EDA veteran with almost 20 years in the industry. He started at Daisy and moved to Cadence, where his focus has been on custom design software. He has a B.S.E.E. from Santa Clara University.

James Lin
Vice President, Technology Infrastructure Group
National Semiconductor Corporation
Mr. Lin has global responsibility for research and development of design technology, including EDA tool development for design automation, design libraries, and intellectual property as well as design collateral such as process and package design kits. Prior to joining National Semiconductor, he held engineering positions at Siliconix, LSI Logic, and a start-up, Austech Microsystems. His working experience includes circuit and logic design, product engineering, and design automation. Lin received a Bachelor of Science degree in electrical engineering from National Chiao-Tung University in Taiwan and a Master of Science degree in electrical engineering from Pennsylvania State University. He has been awarded 13 U.S. patents, and more are pending.

Shrenik Mehta
Chairman
Accellera
Mr. Mehta is also senior director of Frontend Technologies and the OpenSPARC program, Microelectronics, Sun Microsystems. Accelera is the electronics industry organization focused on electronic design automation (EDA) standards.