Different approaches are being used to ensure the economic viability of a chip project. What roles do IP, reuse, designers, design methodologies, and manufacturing options play? How much impact does each have on managing the cost of a packaged IC? How do the different components that contribute to a chip collaborate to ensure the best decisions are made when trading off performance, power, area, and cost? What can be done better? These panelists will debate what can be done to approach IC unit cost from areas other than IP and manufacturing licensing/manufacturing costs.

Adam Traidman President Chip Estimate Corporation

Prior to joining Chip Estimate, Mr. Traidman ran North America West sales at Hier Design, an FPGA design automation company acquired by Xilinx in 2004. His industry experience includes various management and technical roles at Adaptec, Monterey Design Systems, Texas Instruments, and the NASA JPL. He holds a B.S. degree in computer and systems engineering from Rensselaer Polytechnic Institute.

Robert Aitken R&D Fellow ARM

Mr. Aitken's areas of responsibility include library architecture, low power design, and design for manufacturability. He has worked on libraries and modeling for many years at ARM, Artisan, Agilent, and HP. Mr. Aitken has given tutorials and short courses on several subjects at conferences and universities worldwide. He has published more than 50 technical papers and holds a Ph.D. degree from McGill University in Canada.

Walter Ng Vice President, Design Enablement Alliances Chartered Semiconductor Manufacturing

Mr. Ng is responsible for identifying, developing, and executing customer and partner alliances that advance the adoption of Chartered's solutions for the leading-edge and mainstream technology nodes. Previously, he served as senior director of design solutions and was responsible for driving and managing Chartered's relationships with third-party EDA and IP partners. Prior to joining Chartered, Mr. Ng was director of business development of Asia-Pacific operations with Sequence Design. Mr. Ng also worked with Cadence Design Systems and Raytheon's Equipment Development Labs.

Pete Rodriguez Chief Marketing Officer Virage Logic

Mr. Rodriguez is responsible for driving demand on generation initiatives with a focus on establishing and maintaining strategic engagements with Virage Logic's global customers. He also serves as a director for EXAR, a manufacturer of mixed-signal ICs, and previously served as president, CEO, and a director of Xpedion Design Systems, Inc. Mr. Rodriguez also held senior management positions in sales and marketing at Escalade Corporation, senior sales management positions at LSI Logic, and product management and process engineering positions at Aerojet Electronics, Teledyne Microwave, and Siliconix.

Mobashar Yazdani Senior Engineer/Scientist, GS&P, Imaging, and Printing Hewlett-Packard

Mr. Yazdani is in HP's Global Sourcing group, supporting ASIC technology acquirement and development for HP imaging and printing groups worldwide. Prior, he was principal scientist in HP procurement for assessment of silicon providers and managed the ASIC/ASSP technology center in HP supply-chain operations for a number of years. He started at HP in 1988 on the design of its first generation of CMOS RISC processors and on various ASICs for the HP enterprise computer line.