As the speed of serializer/deserializer (SerDes) increases beyond 12.5G, the channels become band-limited, introducing severe inter-symbol interference (ISI). It has become increasingly difficult to support such high speeds within a reasonable power budget. This paper looks at different perspectives of high-speed SerDes design and sees how to combine the techniques to achieve a solution for 25G SerDes. It will look at different signaling formats and modulation schemes and evaluate if they are suitable for high-speed SerDes. Also looked at are equalization schemes, crosstalk cancellation, and burst correcting codes.