Andrew Martwick, Electromagnetics Engineer, Intel

A key component of high-speed serial links is the clock recovery circuit. This circuit looks at the incoming data stream and synthesizes a sampling clock that is then used to recover the data. Traditional communications uses a phase lock loop for this type of circuit, but modern implementations use a cheaper, simpler, lower-power phase interpolation circuit. It is known that the PI circuit is inherently nonlinear, and several models have been proposed to model the frequency response (ref).

In this paper, we provide the block diagram basic operation of the phase interpolation circuit. We simplify the block operation into the phase comparitor (the delta), the sign summation (sigma), and the first-order low pass filter. The Z domain response is provided along with the slew rate limitations of the circuit. The slew rate limit is shown to be the fundamental nonlinearity of the PI. Finally, simulations are shown that allow for adjustable frequency response and loop gain that provide tracking of large phase differences, including two clocks with different spread spectrum domains. The implementation of the filter is a first-order FIR with gain.