In contrast to most chip-to-chip I/O interfaces that use differential signaling, the majority of memory interface designs are based on single-ended signaling such as SSTL or PODL. Extending the data rate for single-ended signaling beyond the current data rate of a few Gbps is becoming very difficult. This paper studies the potential data-rate impact of various signal and power noise components on single-ended signaling systems, using GDDR3/4 memory system as examples. In particular, the performance of various packages, motherboards, coding schemes, and equalization techniques are considered. We show that the crosstalk impact can be mitigated by employing stripline designs, incurring high cost in system design. However, the potential data rate is still limited by SSO noise. The DBI coding scheme introduced lately in GDDR4 reduces SSO noise but only offers marginal system performance gain. Finally, a relative performance gain using various different single-ended signaling options is given.

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